C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 230
![BOARD TARGET/PROTO W/C8051F930](/photos/9/25/92560/c8051f930-tb_sml.jpg)
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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C8051F93x-C8051F92x
SFR Definition 21.17. P1DRV: Port1 Drive Strength
SFR Page = 0xF; SFR Address = 0xA5
SFR Definition 21.18. P2: Port2
SFR Page = All Pages; SFR Address = 0xA0; Bit-Addressable
230
Note: Pin P1.7 is only available in 32-pin devices.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
Reset
Reset
Name
Name
Type
Bit
7:0
Type
7:0
Bit
Bit
Bit
P1DRV[7:0]
Name
P2[7:0]
Name
7
0
7
1
Drive Strength Configuration Bits for
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P1.n Output has low output drive strength.
1: Corresponding P1.n Output has high output drive strength.
Port 2 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
0
1
6
6
Description
5
0
5
1
Rev. 1.1
4
0
4
1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
P1DRV[7:0]
P2[7:0]
R/W
R/W
P1.7–P1.0 (respectively).
Function
Read
3
0
3
1
2
0
2
1
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
1
0
1
1
Write
0
0
0
1
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