C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 306
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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C8051F93x-C8051F92x
26.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not
automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be
cleared by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the
High-Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on
the next match event.
Important Note About Capture/Compare Registers : When writing a 16-bit value to the PCA0
Capture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
306
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
PCA
Timebase
Figure 26.6. PCA High-Speed Output Mode Diagram
Enable
W
M
P
1
6
n
x
C
O
M
E
n
PCA0CPLn
PCA0CPMn
C
A
P
P
n
0 0
PCA0L
C
A
P
N
n
16-bit Comparator
M
A
T
n
O
G
T
n
W
P
M
n
0 x
E
C
C
F
n
PCA0CPHn
PCA0H
Rev. 1.1
Match
Toggle
C
F
C
R
TOGn
0
1
PCA0CN
0
1
CEXn
C
C
F
2
C
C
F
1
C
C
F
0
PCA Interrupt
Crossbar
Port I/O
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