C8051F930-TB Silicon Laboratories Inc, C8051F930-TB Datasheet - Page 72
C8051F930-TB
Manufacturer Part Number
C8051F930-TB
Description
BOARD TARGET/PROTO W/C8051F930
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F930-TB
Contents
Board
Processor To Be Evaluated
C8051F930
Processor Series
C8051F9xx
Data Bus Width
8 bit
Interface Type
I2C, UART, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
0.9 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F930
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1472
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C8051F93x-C8051F92x
SFR Definition 5.1. ADC0CN: ADC0 Control
SFR Page = 0x0; SFR Address = 0xE8; bit-addressable;
72
Name
Reset
Type
Bit
2:0
7
6
5
4
3
Bit
ADC0CM[2:0]
BURSTEN
AD0BUSY
AD0WINT
AD0INT
AD0EN
AD0EN
Name
R/W
7
0
BURSTEN
ADC0 Enable.
0: ADC0 Disabled (low-power shutdown).
1: ADC0 Enabled (active and ready for data conversions).
ADC0 Burst Mode Enable.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
ADC0 Conversion Complete Interrupt Flag.
Set by hardware upon completion of a data conversion (BURSTEN=0), or a burst of conver-
sions (BURSTEN=1). Can trigger an interrupt. Must be cleared by software.
ADC0 Busy.
Writing 1 to this bit initiates an ADC conversion when ADC0CM[2:0] = 000.
ADC0 Window Compare Interrupt Flag.
Set by hardware when the contents of ADC0H:ADC0L fall within the window specified by
ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL. Can trigger an interrupt. Must be cleared by
software.
ADC0 Start of Conversion Mode Select.
Specifies the ADC0 start of conversion source.
000: ADC0 conversion initiated on write of 1 to AD0BUSY.
001: ADC0 conversion initiated on overflow of Timer 0.
010: ADC0 conversion initiated on overflow of Timer 2.
011: ADC0 conversion initiated on overflow of Timer 3.
1xx: ADC0 conversion initiated on rising edge of CNVSTR.
R/W
6
0
AD0INT
R/W
5
0
AD0BUSY AD0WINT
Rev. 1.1
W
4
0
Function
R/W
3
0
2
0
ADC0CM
R/W
1
0
0
0
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