IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 10

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Introduction
1–4
Nios II C2H Compiler User Guide
implementing entire systems on a chip. As a result, the tools available to
FPGA and software designers have undergone continual transformation
of design-entry methods and behind-the-scenes optimization techniques.
This transformation has enabled designers to create ever-bigger designs
to fill ever-growing chip capacity.
Recent years have seen the broad acceptance of FPGA-based
microprocessor cores, such as the Nios II processor, and system
integration tools, such as SOPC Builder. These tools made it possible, for
the first time, to implement C code easily in an FPGA-based system.
Optimizing and evolving these tools is a natural next step for C-based
design on FPGAs. This background sets the stage for practical advances
in C-to-hardware technologies based on an established design
methodology.
FPGA-based processors and system integration tools offer new ways to
improve the performance of embedded systems. Traditional methods to
increase performance of processor systems include:
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FPGA-based processor systems enable additional optimization
techniques capable of achieving much higher performance gains. These
techniques include:
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■
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The application of these techniques relies on real-world tools to
implement them. Consequently, the acceptance of these techniques has
grown as system integration tools, such as Altera's SOPC Builder, have
matured and gained acceptance. It is a fortunate coincidence that these
techniques also directly benefit C-to-gates methodologies. Flexibility of
hardware architecture and ease of implementation are at the heart of the
appeal of C-to-gates tools.
Increasing clock speed
Upgrading to a processor with higher Dhrystone MIPS-per-
megahertz performance
Coding critical sections of software in assembly language
The ability to rapidly alter the FPGA design, allowing you to
prototype a variety of architectures
The ability to divide and conquer processing tasks by instantiating
multiple processor cores
The ability to augment a processor with custom hardware that off-
loads processor-intensive operations into the FPGA fabric
The ability to adjust memory architecture for memory-intensive
operations, such as using high-speed, point-to-point connections to
fast memory buffers
9.1
Altera Corporation
November 2009