IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 55

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Example 3–7. Local Array That Uses 4 KBytes of On-Chip Memory Inside Accelerator
int my_func(int a_parameter)
{
}
Memory
Accesses
Altera Corporation
November 2009
int data[1024]; // 1K 4-byte ints
... // Body of the function
return data[0];
Example 3–7
the accelerator to store array data[1024]. Because this memory buffer
is large, it translates to an embedded memory block.
Global and Static Variables
Global and static variables must persist outside the scope of the
accelerated function, and they have real addresses accessible by the
processor. For this reason, global and static variables are stored in
memory that the processor can access, outside of the accelerator
hardware. In other words, the C2H Compiler does not affect the location
of these variables; it creates logic in the accelerator capable of accessing
the memory where the variables reside.
References to global and static variables translate to master ports in
hardware, which enable access to a given variable's specific memory
location. For further details, refer to section
page
Hardware accelerators generated by the C2H Compiler use Avalon-MM
master ports to access memory, similar to the Nios II processor and other
SOPC Builder components. The Altera
tool handles the task of physically connecting both accelerators and
processors to memory, and creating arbitration logic. As a result, the
3–15.
•
•
•
Avalon-MM master ports are generated even when local arrays
(such as the ones discussed here) are referenced. These master
ports only connect to internal slave ports inside the accelerator.
However, the master ports do appear in the C2H Compiler build
report.
demonstrates the creation of a local 4 kbyte memory inside
Arrays that are initialized
Global variables
Static variables
9.1
®
SOPC Builder system integration
C-to-Hardware Mapping Reference
Nios II C2H Compiler User Guide
“Memory Accesses” on
3–15