IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 26

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Tutorial
Tutorial
2–4
Nios II C2H Compiler User Guide
f
OpenCore Plus hardware evaluation supports the tethered mode of
operation for C2H. In tethered mode the accelerator runs indefinitely, as
long as the target board remains connected to the host computer by an
Altera download cable
You need to purchase a license for the Nios II C-to-Hardware
Acceleration Compiler only when you are completely satisfied with the
functionality and performance of your accelerated Nios II system, and
want to take your design to production.
For more information on OpenCore Plus hardware evaluation, see
AN 320: OpenCore Plus Evaluation of
This section guides you through the steps to accelerate a function using
the C2H Compiler. You create a new software project in the Nios II IDE
using the provided example design files, accelerate a function, and
observe the performance improvement.
This tutorial guides you through the steps to implement the example
design. These steps start with a C source file and end with a running
application that includes an accelerated function. The steps you perform
are described in the following sections:
1.
2.
3.
4.
5.
6.
7.
Tutorial Design
The hardware design for this tutorial is based on the standard hardware
example design provided with the Nios II EDS. The software design is a
C file named dma_c2h_tutorial.c, which is available for download from
the Altera website. You can run the tutorial design on any Nios
development board available from Altera.
“Set up the Hardware for the Project” on page 2–5
“Create the Software Project” on page 2–6
“Run the Project as Software Only” on page 2–7
“Create and Configure a Hardware Accelerator” on page 2–8
“Rebuild the Project” on page 2–10
“Observe Results in the Report File” on page 2–11
“Observe the Accelerator in SOPC Builder” on page 2–14
9.1
Megafunctions.
Altera Corporation
November 2009