IPT-C2H-NIOS Altera, IPT-C2H-NIOS Datasheet - Page 91

• Manufacturer Part Number: IPT-C2H-NIOS
• Description: C2H COMPILER FOR NIOS II
• Manufacturer: Altera
• Series: Nios®IIr
• Type: Nios IIr

Specifications of IPT-C2H-NIOS

• Function: C to Hardware Compiler
• License: Initial License
• Software Application: IP CORE, NIOS Processor And Functions
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Resource
Sharing
Altera Corporation
November 2009
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Table 3–6. Sharable Resource
Dereference or
Operator
Memory Access
Multiply
Divide
Modulo
Left Shift
Right Shift
Description
The C2H Compiler is capable of sharing resources which consume
significant amounts of logic. A resource only becomes shared if it is
under-utilized. In other words, the C2H Compiler only shares a resource
if the performance of accelerator is not affected.
resources that can be shared automatically by the C2H Compiler.
- Multiple dereferences to access data from the same Avalon-MM
memory port
- Multiple dereferences occurring within the same level in the
algorithm (function or loop)
- Loop CPLI must not increase
- Promoted data width (32 or 64 bit) must be the same for all
multiplications. The promoted data width is shown in the C2H report.
- Multiplications occurring within the same level in the algorithm
(function or loop)
- Both operands must be either signed or unsigned.
- Loop CPLI must not increase
- Promoted data width (32 or 64 bit) must be the same for all divisions.
The promoted data width is shown in the C2H report.
- Divisions occurring within the same level in the algorithm (function
or loop)
- Both operands must be either signed or unsigned.
- Loop CPLI must not increase
- Promoted data width (32 or 64 bit) must be the same for all modulo
operations. The promoted data width is shown in the C2H report.
- Modulo operations occurring within the same level in the algorithm
(function or loop)
- Both operands must be either signed or unsigned.
- Loop CPLI must not increase
- Promoted data width (32 or 64 bit) must be the same for all left shift
operations. The promoted data width is shown in the C2H report.
- Left shift operations occurring within the same level in the algorithm
(function or loop)
- Both operands must be either signed or unsigned.
- Loop CPLI must not increase
- Promoted data width (32 or 64 bit) must be the same for all right shift
operations. The promoted data width is shown in the C2H report.
- Right shift operations occurring within the same level in the
algorithm (function or loop)
- Both operands must be either signed or unsigned.
- Loop CPLI must not increase
9.1
Required Conditions
C-to-Hardware Mapping Reference
Nios II C2H Compiler User Guide
Table 3–6
lists all of the
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