AD9954/PCB Analog Devices Inc, AD9954/PCB Datasheet - Page 21

• Manufacturer Part Number: AD9954/PCB
• Description: BOARD EVAL FOR AD9954
• Manufacturer: Analog Devices Inc

Specifications of AD9954/PCB

• Rohs Status: RoHS non-compliant

SYNCHRONIZATION—REGISTER UPDATES (I/O
UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9954 is synchronous to the SYNC_CLK
signal (supplied externally to the user on the SYNC_CLK pin).
The I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-four frequency divider
to produce the SYNC_CLK signal. The SYNC_CLK signal is
made available to the system on the SYNC_CLK pin. This
enables synchronization of external hardware with the device’s
internal clocks. This is accomplished by providing the SYNC_CLK
signal as an output that external hardware can then use to
synchronize against.
I/O BUFFERS
I/O UPDATE
REGISTERS
SYNC_CLK
SYSCLK
DATA IN
DATA IN
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM
THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
N
N – 1
TO CORE LOGIC
A
SYSCLK
Figure 24. I/O Synchronization Timing Diagram
Figure 23. I/O Synchronization Block Diagram
B
Q
D
REGISTER
MEMORY
OSK
N + 1
Rev. B | Page 21 of 40
DETECTION
SYNC_CLK
GATING
LOGIC
÷4
EDGE
Q
I/O BUFFER
D
LATCHES
PS<1:0>
The I/O update signal coupled with SYNC_CLK is used to
transfer internal buffer contents into the control registers. The
combination of the SYNC_CLK pin and the I/O UPDATE pin
provides the user with constant latency relative to SYSCLK and
ensures phase continuity of the analog output signal when a
new tuning word or phase offset value is asserted.
Figure 23 and Figure 24 demonstrate an I/O update timing
cycle and synchronization.
Synchronization logic notes include the following:
 The I/O update signal is edge detected to generate a single-
 The I/O UPDATE pin is set up and held around the rising
cycle clock signal that drives the register bank flops. The I/O
update signal has no constraints on duty cycle. The minimum
low time on I/O update is one SYNC_CLK clock cycle.
edge of SYNC_CLK. Setup and hold time specifications can
be found in Table 2.
N
Q
D
0
SYNC_CLK
DISABLE
I/O UPDATE
SCLK
SDIO
CS
N + 2
N + 1
AD9954