AD9954/PCB Analog Devices Inc, AD9954/PCB Datasheet - Page 26

• Manufacturer Part Number: AD9954/PCB
• Description: BOARD EVAL FOR AD9954
• Manufacturer: Analog Devices Inc

Specifications of AD9954/PCB

• Rohs Status: RoHS non-compliant

AD9954
Table 12. Register Map—When Linear Sweep Enable Bit Is False (CFR1<21> = 0)
Note that the RAM Enable Bit CFR1<31> only activates the RAM itself, not the RAM segment control words.
Register
Name
(Serial
Address)
Control
Function
Register
No.1
(CFR1)
(0x00)
Control
Function
Register
No. 2
(CFR2)
(0x01)
Amplitude
Scale
Factor (ASF)
(0x02)
Amplitude
Ramp Rate
(ARR)
(0x03)
Frequency
Tuning
Word
(FTW0)
(0x04)
Phase
Offset Word
(POW0)
(0x05)
Frequency
Tuning
Word
(FTW1)
(0x06)
Profile 0
RAM
Segment
Control
Word No. 0
(RSCW0)
(0x07)
Bit
Range
<7:0>
<15:8>
<23:16>
<31:24>
<7:0>
<15:8>
<23:16>
<7:0>
<15:8>
<7:0>
<7:0>
<15:8>
<23:16>
<31:24>
<7:0>
<15:8>
<7:0>
<15:8>
<23:16>
<31:24>
<7:0>
<15:8>
<23:16>
<31:24>
<39:32>
(MSB)
Bit 7
Digital
Power-
Down
SRR Load
Enable
Automatic
Sync
Enable
RAM
Enable
Speed Control<1:0>
Auto Ramp Rate
Not Used<1:0>
RAM Segment 0 Mode
Control<2:0>
Bit 6
Comp
Power-
Down
AutoClr
Freq
Accum
Software
Manual
Sync
RAM
Destination
RAM Segment 0 Beginning Address<5:0>
Not Used
REFCLK Multiplier
Bit 5
DAC
Power-
Down
AutoClr
Phase
Accum
Linear
Sweep
Enable
RAM Segment 0 Address Ramp Rate<15:8>
RAM Segment 0 Address Ramp Rate<7:0>
Internal Profile Control<2:0>
Amplitude Scale Factor Register<7:0>
Frequency Tuning Word No. 0<23:16>
Frequency Tuning Word No. 0<31:24>
Frequency Tuning Word No. 1<23:16>
Frequency Tuning Word No. 1<31:24>
Amplitude Ramp Rate Register<7:0>
Frequency Tuning Word No. 0<15:8>
Frequency Tuning Word No. 1<15:8>
RAM Segment 0 Final Address<7:0>
Frequency Tuning Word No. 0<7:0>
Frequency Tuning Word No. 1<7:0>
Rev. B | Page 26 of 40
Phase Offset Word No. 0<7:0>
No-Dwell
Active
Bit 4
Clock
Input
Power-
Down
Sine/
Cosine
Select
Not Used
Amplitude Scale Factor Register<13:8>
Not Used
Phase Offset Word No. 0<13:8>
Bit 3
External
Power-
Down
Mode
Clear
Freq
Accum
Not
Used
High
Speed
Sync
Enable
RAM Segment 0 Beginning Address<9:6>
Bit 2
Linear
Sweep
No-
Dwell
Clear
Phase
Accum
Not Used
Load ARR
Control
VCO
Range
Hardware
Manual
Sync
Enable
Bit 1
SYNC_CLK
Disable
SDIO
Input
Only
Not Used
OSK
Enable
XTAL
OUT
Enable
Final Address<9:8>
RAM Segment 0
Charge Pump
Current<1:0>
(LSB)
Bit 0
Not
Used
LSB First
Not
Used
Auto
OSK
Enable
Not
Used
0x00
0x00
0x00
0x18
0x00
0x00
PS0 = 0
PS1 = 0
PS0 = 0
PS1 = 0
Default
Value Or
Profile
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PS0 = 0
PS1 = 0
PS0 = 0
PS1 = 0
PS0 = 0
PS1 = 0