AD9954/PCB Analog Devices Inc, AD9954/PCB Datasheet - Page 22

• Manufacturer Part Number: AD9954/PCB
• Description: BOARD EVAL FOR AD9954
• Manufacturer: Analog Devices Inc

Specifications of AD9954/PCB

• Rohs Status: RoHS non-compliant

AD9954
Synchronizing Multiple AD9954s
There are three modes of synchronization available to the user:
an automatic synchronization mode, a software-controlled
manual synchronization mode, and a hardware-controlled
manual synchronization mode. The following requirements
apply to all modes. First, all units must share a common clock
source. Trace lengths and path impedance of the clock tree must
be designed to keep the phase delay of the different clock branches
as closely matched as possible. Second, the I/O update signal’s
rising edge must be provided synchronously to all devices being
synchronized. Finally, the DVDD_I/O supply should be set to
3.3 V for all devices that are to be synchronized. AVDD and
DVDD should be left at 1.8 V.
In automatic synchronization mode, one device is chosen as a
master, the other device(s) is slaved to this master. All slaves
automatically synchronize their internal clocks to the SYNC_CLK
output signal of the master device. Use the automatic
synchronization bit (CFR1<23>) to configure each slave.
Connect the SYNC_IN input(s) to the master SYNC_CLK
output. Slave devices continuously update the phase relationship of
their SYNC_CLK until it is in phase with the SYNC_IN input.
The high speed sync enhancement enable bit (CFR2<11>) must
be programmed correctly.
In software manual synchronization mode, the user can force
the device to advance the SYNC_CLK rising edge one SYSCLK
cycle (¼ SYNC_CLK period). Manual synchronization mode
is established using the slave device’s software manual
synchronization bit (CFR1<22>). See the bit description in
Table 12 for more details.
In hardware manual synchronization mode, the SYNC_IN
input pin is configured such that it now advances the rising edge
of the SYNC_CLK signal each time the device detects a rising edge
on the SYNC_IN pin. Hardware manual synchronization mode is
established using the hardware manual synchronization bit
(CFR2<10>). See the bit description in Table 12 for more details.
Using a Single Crystal to Drive Multiple AD9954 Clock
Inputs
The AD9954 crystal oscillator output signal is available on the
CRYSTAL OUT pin, enabling one crystal to drive multiple
AD9954s. To drive multiple AD9954s with one crystal, the
CRYSTAL OUT pin of the AD9954 using the external crystal
should be connected to the REFCLK input of the other AD9954.
The CRYSTAL OUT pin must be enabled using the CRYSTAL
OUT Pin Active Bit CFR2<9>. The drive strength of the
CRYSTAL OUT pin is fairly low; therefore, the signal
should be buffered if multiple loads are being driven.
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RAM
The AD9954 incorporates a block of SRAM. The RAM is a
bidirectional single port. Read and write operations cannot
occur simultaneously. Write operations to the serial I/O port
take precedence; therefore, if an attempt to write to RAM is
made during a read operation, the read operation is halted. The
RAM is configurable using the RAM Segment Control Word<7:5>
and data in the control function register.
Using the RAM enable bit (CFR1<31>), the RAM output can be
enabled to drive the input to either the phase accumulator or
the phase offset adder; the RAM destination bit (CFR1<30>)
sets the routing. When the RAM output drives the phase
accumulator, the phase offset word (POW, Address 0x05) drives
the phase-offset adder. Conversely, when the RAM output
drives the phase-offset adder, the frequency tuning word (FTW,
Address 0x04) drives the phase accumulator. When CFR1<31>
disables the RAM, it is inactive unless being written to via the
serial port. The RAM is mapped into one of four profiles
determined by the PS1 and PS0 input pins. Note that these
profiles may overlap. For example, Profile 0 may use RAM
Address Location 0 to Address Location 12, and Profile 1 may use
RAM Address Location 5 to Address Location 20, and so forth.
All RAM write or read operations to/from the RAM are
controlled by the PS1 and PS0 input pins and the respective
RAM segment control word. To write to the RAM, a RAM
segment must be defined in a RAM segment control word. The
RAM segment that was defined must then be selected by use of
the profile select pins, PS0 and PS1. With the correct RAM
segment selected, the special instruction byte of 0xB0 should
be sent. When the instruction byte to write to the RAM is sent
to the part, the serial port controller immediately polls the
corresponding RAM segment control word. From this register,
the serial port controller makes note of the start address and the
stop address. It then calculates how many entries there are in
the segment, and how many bytes of data to expect. After
sending the special instruction byte of 0xB0, the user must send
all RAM entries for the currently selected profile to the part.
For example, consider a case where RAM Segment 2 begins at
Address 21 and ends at Address 120. First, write to RAM Segment
Control Word 2 with a starting address of 21, with a stop address
of 120, and specify a ramp rate and a mode of operation. Next, set
PS1 to 1 and PS0 to 0 to select RAM Segment 2 and then send
the instruction byte of 0xB0. The part is now ready to put the first
32-bit word into the RAM at Address 21, to expect 100 32-bit
words, and to store the last one at Address 120. It automatically
controls sending the data from the serial port to the correct RAM
address. Therefore, precede sending 100 32-bit words of data to
the part. After the 3200th SCLK cycle, the write operation is
complete, and all 100 words are stored in the RAM, from
Address 21 to Address 120.