AD9954/PCB Analog Devices Inc, AD9954/PCB Datasheet - Page 31

• Manufacturer Part Number: AD9954/PCB
• Description: BOARD EVAL FOR AD9954
• Manufacturer: Analog Devices Inc

Specifications of AD9954/PCB

• Rohs Status: RoHS non-compliant

CFR2<2>: VCO Range Control Bit
CFR2<2> = 0 (default), VCO operates between 100 MHz and
250 MHz.
CFR2<2> = 1, VCO operates between 250 MHz and 400 MHz.
CFR2<1:0>: Charge Pump Current Control Bits
These bits are used to control the current setting on the charge
pump. The default setting, CFR2<1:0>, sets the charge pump
current to the default value of 75 μA. For each bit added, 25 μA
of current is added to the charge pump current:
01 = 100 μA, 10 = 125 μA, and 11 = 150 μA.
OTHER REGISTER DESCRIPTIONS
Amplitude Scale Factor (ASF)
The ASF register stores the 2-bit auto ramp rate speed value and
the 14-bit amplitude scale factor used in the output shaped
keying (OSK) operation. In auto-OSK operation, ASF<15:14>
tells the OSK block how many amplitude steps to take for each
increment or decrement. ASF<13:0> sets the maximum value
achievable by the OSK internal multiplier. In manual OSK
mode, ASF<15:14> has no effect. ASF<13:0> provide the output
scale factor directly. If the OSK is disabled using CFR1<25>,
this register has no effect on device operation.
Amplitude Ramp Rate (ARR)
The ARR register stores the 8-bit amplitude ramp rate used in
the auto-OSK mode. See the Amplitude Control Options
section for details.
Frequency Tuning Word 0 (FTW0)
The frequency tuning word is a 32-bit register that controls the
rate of accumulation in the phase accumulator of the DDS core.
Its specific role is dependent on the device mode of operation.
Phase Offset Word (POW)
The phase offset word is a 14-bit register that stores a phase
offset value. See the Phase Offset Word Mux section for
additional details.
Frequency Tuning Word 1 (FTW1)
The frequency tuning word is a 32-bit register that sets the
upper frequency in a linear sweep operation.
Register 0x07 and Register 0x08 are multifunctional registers.
Negative and Positive Linear Sweep Control Word
(NLSCW and PLSCW)
When linear sweep bit is enabled, Register 0x07 provides the
negative linear sweep control word (NLSCW) and Register 0x08
provides the positive linear sweep control word (PLSCW). Each
of the linear sweep control words contains a 32-bit delta frequency
tuning word (FDFTW and RDFTW) and an 8-bit sweep ramp
rate word (FSRRW and RSRRW). See the Modes of Operation
section for more details.
Rev. B | Page 31 of 40
RAM Segment Control Words (RSCW0, RSCW1, RSCW2,
and RSCW3)
When linear sweep is disabled, Register 0x07, Register 0x08,
Register 0x09, and Register 0x0A act as the RAM segment
control words for each of the RAM segments. Each of the RAM
segment control words is comprised of a RAM segment address
ramp rate, a final address value, a beginning address value, a
RAM segment mode control, and a no-dwell bit. Note the
discontinuities of the address registers, since they may make
programming a little more challenging.
RAM Segment Address Ramp Rate, RSCW<39:24>
For RAM modes that step through address values, such as
ramping, this 16-bit word defines the number of SYNC_CLK
cycles the RAM controller dwells at each address. A value of 0 is
invalid. Any other value from 1 to 65,535 can be used.
RAM Segment Final Address RSCW<9:8>, RSCW<23:16>
This discontinuous 10-bit sequence defines the final address
value for the given RAM segment. The order in which the bits
are previously listed is MSB first: RSCW<9> is the MSB and
RSCW<16> is the LSB of the final address value.
RAM Segment Beginning Address RSCW<3:0>,
RSCW <15:10>
This discontinuous 10-bit sequence defines the final address
value for the given RAM segment. The order in which the bits
are previously listed is MSB first: RSCW<3> is the MSB and
RSCW<10> is the LSB of the final address value.
RAM Segment No-Dwell Bit RSCW<4>
This bit sets the no-dwell feature of sweeping profiles. In
profiles that sweep from a defined beginning to a defined end,
the RAM controller can either dwell at the final address until
the next profile is selected or, when this bit is set, the RAM
controller returns to the beginning address and dwells there
until the next profile is selected.
RAM Segment Mode Control RSCW<7:5>
This 3-bit sequence determines the RAM segment’s mode of
operation. There are only five possible RAM modes, so only
values of 0 to 4 are valid (see Table 7).
AD9954