AD9954/PCB Analog Devices Inc, AD9954/PCB Datasheet - Page 33

• Manufacturer Part Number: AD9954/PCB
• Description: BOARD EVAL FOR AD9954
• Manufacturer: Analog Devices Inc

Specifications of AD9954/PCB

• Rohs Status: RoHS non-compliant

DETAILED PROGRAMMING EXAMPLES
SINGLE-TONE MODE
In this example, the part is programmed to output a 122 MHz
single-tone carrier, the device is clocked with a 20 MHz crystal
oscillator, and the clock multiplier is used to push the internal
system clock up to 400 MHz. Phase offsets are then added to
the carrier.
The programming steps include the following:
1. Write to Control Register 1 instructing the part to autoclear
2. Write to Control Register 2 setting the clock multiplier value
3. Calculate the tuning word to generate a 122 MHz output
LINEAR SWEEP MODE
In this example, the part is programmed to generate a chirp
from 61.53 MHz to 62.73 MHz. The chirp up is in 1.20 μs,
the chirp down is in 1.8 μs, and the chirp is made as finely
linearized as possible. Therefore, users must calculate and
program:
 FTW0 for 61.53 MHz (the start frequency)
 FTW1 for 62.73 MHz (the stop frequency)
 CFR1 to put the part into linear sweep mode
 The positive linear sweep control word (PLSCW), to make as
 The negative linear sweep control word (NLSCW), to make
linearized a chirp in 1.20 μs
as linearized a chirp in 1.80 μs
the phase accumulator whenever the phase offset word
changes and issues an I/O update. Set Bit 13 in the CFR1
register. The address for CFR1 is 0; therefore, an instruction
byte of 0x00 is sent and 0x00 00 00 20 for data. Note that
users must write to all four bytes of the register.
to 20, and the VCO range bit to its upper value. In CFR2,
Bit 7 to Bit 3 control the multiply value. To get a multiplied
value of 20 from 5 bits, the binary value is 10100. As
previously mentioned, also send Bit 2 to put the VCO into its
upper range (to get 400 MHz). Therefore, the instruction byte
is 0x01 and 0x00 00 A4 for data.
from a 400 MSPS clock, load it into FTW0, and latch the
data written to the I/O buffers into their respective registers.
The frequency tuning word equation becomes (122 MHz/
400 MHz) × 2
Instruction Byte 0x04 and four data bytes of 0x4E 14 7A E1.
Issue an I/O update, which transfers the data into the part.
Whenever a phase change is desired, calculate and write the
phase offset word to the part and issue an I/O update. For
example, if the first value is 45°, the phase offset word is
(45/360) × 2
instruction byte of 0x05 and Data Byte 0x0800. When an
I/O update is issued, the phase accumulator clears, which
starts it from a known phase of 0°. It again accumulates at a
122 MHz rate, except now phase shifting each and every
sample by 45°.
14
, or in decimal, 2048. Therefore, write an
32
, which yields 0x4E 14 7A E1. Send the
Rev. B | Page 33 of 40
The last example programmed the clock multiplier; therefore,
start with a 400 MSPS clock. FTW0 is (61.53/400) × 2
0x27611340, and FTW1 is (62.73/400) × 2
To turn the linear sweep on, set CFR1<21>.
The PLSCW and NLSCW are five bytes wide: one byte for the
ramp rate and four bytes for the incremental frequency value.
To begin, calculate the ramp rate, and cover 1.2 MHz on both
sweeps. The ramp rate tells the part how many SYNC_CLK
cycles (for SYSCLK cycles) to send at each incremental value.
When the shortest time possible is spent at each incremental
frequency, the most linearized sweep is achieved; therefore, the part
should only spend one SYNC_CLK period at each incremental
frequency, which ensures that the smallest frequency steps possible
are taken. For a 400 MSPS SYSCLK, the result is a 100 MHz
SYNC_CLK rate or a 10 ns SYNC_CLK period. This means on the
finest resolution, 120 incremental steps squeeze into the rising
sweep (1.2 μs/10 ns) and 180 on the falling sweep (1.8 μs/10 ns).
For the rising delta frequency, a 1.2 MHz/120 steps is calculated,
which means each step is approximately 10 kHz for the rising
delta frequency and approximately 666.6666 Hz for the falling
delta frequency. The logic in the linear sweep block ensures that
FTW1 on a rising sweep or FTW0 on a falling sweep is not
exceeded. If the exact incremental tuning word is not achieved
using the 32-bit resolution, round up, not down, to ensure the
entire range during the sweep is covered. To calculate the rising
delta frequency word, simply calculate (10 K/400 M) × 2
0x0001A36F. Combining the rising ramp rate, first byte, and the
rising delta frequency, the second byte to fifth byte yields the
PLSCW: 0x010001A36F. Likewise, the NLSCW works out to
0x0100001BF4. Table 14 is a summary table of instruction and
data bytes to write to.
Table 14. Linear Sweep Example Write Instructions
Register
CFR1
FTW0
FTW1
NLSCW
RLSCW
RAM MODE
This example programs the RAM. Use the RAM on the AD9954
to simulate the nonlinear filter shape of a Gaussian filter response
on the FSK data. Begin by plotting the filter response from F0 to
F1 and from F1 to F0. The transition time specification (see
Table 1) tells how long it takes to transition from F0 to F1 and
from F1 to F0, either as an actual time value or as a fraction of
the symbol rate. Both ways show how long it can take to change
symbols, and for this application, it is 100 ns. To program the
RAM, decide how many RAM segments to use, program the
RAM segment control word for each of those segments, and
load the RAM data for each of those segments.
Instruction Byte
0x00
0x04
0x06
0x07
0x08
32
or 0x2825AEE6.
Data Byte
0x00200000
0x27611340
0x2825AEE6
0x0100001BF4
0x010001A36F
AD9954
32
or
32
=