EZ80F910200ZCO Zilog, EZ80F910200ZCO Datasheet - Page 16

• Manufacturer Part Number: EZ80F910200ZCO
• Description: KIT DEV FOR EZ80F91 W/C-COMPILER
• Manufacturer: Zilog

Specifications of EZ80F910200ZCO

• Processor To Be Evaluated: eZ80F91
• Interface Type: Ethernet
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3154; EZ80F910200ZCO

eZ80F91 Development Kit
User Manual
11
The description of these five signals are provided below.
When active Low, the EN_Flash input signal enables the
Enable Flash—
Flash chip on the eZ80F91 Module.
When active Low, the FlashWE input signal
Flash Write Enable—
enables write operations on the Flash boot block of the eZ80F91 Module.
When the DIS_IrDA input signal is pulled Low, the IrDA
Disable IrDA—
transceiver, located on the eZ80F91 Module, is disabled. As a result,
UART0 can be used with the RS-232 or the RS-485 interfaces on the
®
eZ80Acclaim!
Development Kit.
F91_WE—
When the F91_WE signal is active Low, internal Flash on the
eZ80F91 Module is enabled for writing. This signal is inverted from the
WP signal of on the eZ80F91 Module.
RTC_V
—
RTC_V
is a test point for the Real Time Clock power sup-
DD
DD
ply.
Peripheral Bus Connector
Figure 6
displays the pin layout of the Peripheral Bus Connector in the
50-pin header, located at position JP1 on the eZ80Acclaim! Development
Kit.
Table 3
on page 13 lists the pins and their functions.
UM014220-0508
eZ80 Development Kit