EZ80F910200ZCO Zilog, EZ80F910200ZCO Datasheet - Page 68

• Manufacturer Part Number: EZ80F910200ZCO
• Description: KIT DEV FOR EZ80F91 W/C-COMPILER
• Manufacturer: Zilog

Specifications of EZ80F910200ZCO

• Processor To Be Evaluated: eZ80F91
• Interface Type: Ethernet
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3154; EZ80F910200ZCO

UM014220-0508
D
C
B
A
VCC
RTC_VDD
GND
CR1
CR1
VL1
VL1
1N5817
1N5817
R28
R28
220
220
50MHz
50MHz
C8
C8
C10
C10
0.1uF
0.1uF
5pF
5pF
C5
C5
220pF
220pF
Y2
Y2
R27
R27
RTC_VDD
C6
C6
0.056uF
0.056uF
200K
200K
D[0:7]
C9
C9
10pF
10pF
C11
C11
12pF
12pF
-BUSREQ
-F91_WP
R38
R38
Y3
Y3
5
5
-TRSTN
-RESET
GND
32.768KHz
32.768KHz
-WAIT
-NMI
TMS
TCK
TDI
R26
R26
499
499
3.3uH
3.3uH
10M
10M
L1
L1
VCC
C12
C12
12pF
12pF
-BUSREQ
-TRSTN
-RESET
-F91_WP
D0
D1
D2
D3
D4
D5
D6
D7
-WAIT
-NMI
TMS
TCK
TDI
CRS
COL
RXER
RXDV
RXD3
RXD2
RXD1
RXD0
RXCLK
TXCLK
144
124
125
135
137
141
140
139
138
136
131
112
122
133
108
113
123
134
39
40
41
42
43
44
45
46
54
57
56
66
67
69
71
55
83
86
85
14
22
31
37
47
59
81
88
98
87
15
23
32
38
48
60
64
72
82
89
99
84
63
62
61
6
7
EZ80F91
EZ80F91
U5
U5
D0
D1
D2
D3
D4
D5
D6
D7
WAIT
BUSREQ
NMI
TMS
TCK
TDI
TRSTN
RESET
WP
MII_CRS
MII_COL
MII_RXER
MII_RXDV
MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0
MII_RXCLK
MII_TXCLK
FILT_IN
XIN
XOUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PLL_VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PLL_VSS
RTC_VDD
RTC_XOUT
RTC_XIN
PA5_PWM1_TOUT1
PA4_PWM0_TOUT0
Figure 24. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY
PD1_RXD0_IRRXD
PD0_TXD0_IRTXD
PA6_PWM2_EC1
PA3_PWM3_OC3
PA2_PWM2_OC2
PA1_PWM1_OC1
PA0_PWM0_OC0
PB0_IC0_EC0
PA7_PWM3
PC6_DCD1
PC5_DSR1
PC4_DTR1
PC1_RXD1
PD6_DCD0
PD5_DSR0
PD4_DTR0
PB7_MOSI
PB6_MISO
PC3_CTS1
PC2_RTS1
PC0_TXD1
PD3_CTS0
PD2_RTS0
HALT_SLP
PB5_ICB3
PB4_ICA3
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
MII_TXER
MII_MDIO
PB3_SCK
TRIGOUT
MII_MDC
BUSACK
PC7_RI1
PD7_RI0
PB1_IC1
PB2_SS
INSTRD
IORQ
MRQ
SDA
TDO
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
CS0
CS1
CS2
CS3
SCL
WR
PHI
RD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
4
4
1
2
3
4
5
8
9
10
11
12
13
16
17
18
19
20
21
24
25
26
27
28
29
30
126
127
128
129
130
132
142
143
49
50
51
52
58
33
34
35
36
110
109
121
120
119
118
117
116
115
114
107
106
105
104
103
102
101
100
97
96
95
94
93
92
91
90
80
79
78
77
76
75
74
73
65
111
53
70
68
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
-IORQ
-MREQ
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
TXD3
TXD2
TXD1
TXD0
TXEN
TXER
MDC
MDI0
-RD
-WR
-CS0
-CS1
-CS2
-CS3
SCL
SDA
-IORQ
-MREQ
-RD
-WR
-BUSACK
-CS0
-CS1
-CS2
-CS3
IICSCL
IICSDA
A[0:23]
PA[0:7]
PB[0:7]
PC[0:7]
PD[0:7]
-HALT_SLP
CLK_OUT
-INSTRD
TDO
TRIGOUT
GND
R22 1K
R22 1K
VCC
R18 10K
R18 10K
C44
C44
0.1uF
0.1uF
C49
C49
0.1uF
0.1uF
C31
C31
0.001uF
0.001uF
C18
C18
0.1uF
0.1uF
VCC
Put caps between pairs of U6, 10:11, 51:52, 59:65
and 71:73 as close to the pins as possible
GND
3
3
-RESET
MDI0
MDC
RXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXER
TXCLK
TXD3
TXD2
TXD1
TXD0
TXEN
TXER
COL
CRS
GND
C45
C45
0.1uF
0.1uF
C50
C50
0.1uF
0.1uF
C32
C32
0.001uF
0.001uF
C19
C19
0.1uF
0.1uF
VCC
GND
14
15
16
17
18
19
20
21
22
30
23
24
25
26
29
31
33
40
39
38
37
34
32
41
42
1
2
3
5
7
8
9
C46
C46
0.1uF
0.1uF
C51
C51
0.1uF
0.1uF
C33
C33
0.001uF
0.001uF
C20
C20
0.1uF
0.1uF
U6
U6
AM79C874
AM79C874
PCSB
ISODEF
ISO
REFCLK
BURN_IN
RST
PWRDN
PHYAD4_0RXD-
PHYAD3_10RXD+
PHYAD2_10TXD++
PHYAD1_10TXD-
PHYAD0_10TXD--
GPIO0_10TXD--
GPIO1_TP125
MDIO
MDC
RXCLK
RXD3
RXD2
RXD1
RXD0
RXDV
RXER_RXD4
TXCLK_PCSBPCLK
TXD3
TXD2
TXD1
TXD0
TXEN
TXER_TXD4
COL
CRS
VCC
GND
C47
C47
0.1uF
0.1uF
C52
C52
0.1uF
0.1uF
C34
C34
0.001uF
0.001uF
C21
C21
0.1uF
0.1uF
C48
C48
0.1uF
0.1uF
C53
C53
0.1uF
0.1uF
C35
C35
0.001uF
0.001uF
C22
C22
0.1uF
0.1uF
VCC
LESPD1_LEDTXA_CLK25EN
LEDSPD0_LEDBTA_FXSEL
C36
C36
0.001uF
0.001uF
C23
C23
0.1uF
0.1uF
GND
LEDLNK_LED_10LNK
CPU and PHY
LECOL_SCRAMEN
LEDDPX_LEDTXB
VCC
LEDRX_LEDSEL
LEDTX_LEDBTB
2
2
TEST1_FXR+
C37
C37
0.001uF
0.001uF
C24
C24
0.1uF
0.1uF
TEST3_SDI+
TEST0_FXR-
VCC
TECH_SEL2
TECH_SEL1
TECH_SEL0
R34
R34
330
330
ANEGA
TEST2
IBREF
RPTR
INTR
FXT+
XTL+
FXT-
XTL-
RX+
TX+
RX-
TX-
C38
C38
0.001uF
0.001uF
C25
C25
0.1uF
0.1uF
43
53
54
55
56
72
61
44
45
46
47
48
57
58
62
68
67
66
69
70
74
75
77
78
64
63
R35
R35
330
330
ZiLOG, Inc.
ZiLOG, Inc.
ZiLOG, Inc.
532 Race Street. San Jose,CA 95126. 408.558.8500
532 Race Street. San Jose,CA 95126. 408.558.8500
532 Race Street. San Jose,CA 95126. 408.558.8500
Title
Title
Title
Size
Size
Size
Date:
Date:
Date:
R31 49.9
R31 49.9
B
B
B
R11 49.9
R11 49.9
-LEDRX
-LEDLNK
C39
C39
0.001uF
0.001uF
C26
C26
0.1uF
0.1uF
eZ80F91 Ethernet Module.
eZ80F91 Ethernet Module.
eZ80F91 Ethernet Module.
Document Number
Document Number
Document Number
Wednesday, August 01, 2007
Wednesday, August 01, 2007
Wednesday, August 01, 2007
R32
R32
R33
R33
R21
R21
R24
R24
C15
C15
0.1uF
0.1uF
This schematic reflects the
assembly rev B of the
module.
The FLASH memory on page 3
was changed to AM29008B for
Rev D schematic.
0
0
0
0
49.9
49.9
C40
C40
0.001uF
0.001uF
C27
C27
0.1uF
0.1uF
49.9
49.9
eZ80F91 Development Kit
R19
R19
R23
R23
C16
C16
0.1uF
0.1uF
-LEDRX
-LEDLNK
0
0
96C0879-001
96C0879-001
96C0879-001
C41
C41
0.001uF
0.001uF
C28
C28
0.1uF
0.1uF
0
0
R13
R13
10K
10K
Y1
Y1
25 MHz
25 MHz
R14
R14
10K
10K
Sheet
Sheet
Sheet
1
1
R25
R25
C42
C42
0.001uF
0.001uF
C29
C29
0.1uF
0.1uF
R15
R15
10K
10K
C4 18pF
C4 18pF
C7 18pF
C7 18pF
Schematic Diagrams
10K
10K
2
2
2
10
11
12
1
4
2
3
5
6
8
9
VCC
User Manual
HFJ11-2450E-L11
HFJ11-2450E-L11
GND
VCC
P2
P2
TX+
TXCT
TX-
RX+
RXCT
RX-
GND
AN1
CT1
AN2
CT2
R16
R16
10K
10K
C43
C43
0.001uF
0.001uF
C30
C30
0.1uF
0.1uF
of
of
of
GND
GND
VCC
C17
C17
0.1uF
0.1uF
10K 0.1%
10K 0.1%
R17
R17
3
3
3
Rev
Rev
Rev
D
D
D
D
C
B
A
63