EZ80F910200ZCO Zilog, EZ80F910200ZCO Datasheet - Page 34
EZ80F910200ZCO
Manufacturer Part Number
EZ80F910200ZCO
Description
KIT DEV FOR EZ80F91 W/C-COMPILER
Manufacturer
Zilog
Datasheet
1.EZ80F910200ZCO.pdf
(78 pages)
Specifications of EZ80F910200ZCO
Processor To Be Evaluated
eZ80F91
Interface Type
Ethernet
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3154
EZ80F910200ZCO
EZ80F910200ZCO
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eZ80F91 Development Kit
User Manual
29
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).
On-Chip SRAM
The eZ80F91 device on the eZ80F91 Module contains 8 KB of on-chip
SRAM. Upon power-up, this SRAM is enabled and mapped to address
. Using the RAM Address Register, this 8 KB memory can be
FFC000h
mapped to the top of any 64 KB block. It can also be disabled. Refer to
eZ80F91 MCU Product Specification (PS0192) for more information.
Flash Memory
The eZ80F91 Development Kit allows off-chip Flash memories between
1 MB and 4 MB. This Flash memory is entirely located on the eZ80F91
Module (as footprint only; as shipped from the factory, external Flash is
not installed).
Memory Map
®
A memory map of the eZ80Acclaim!
Development Kit and the eZ80F91
Module is displayed in
Figure
10. Flash memory and SRAM on the
eZ80F91 Module are addressed when CS0 and CS1 are active Low.
SRAM on the eZ80Acclaim! Development Kit is addressed when CS2 is
active Low.
Refer to eZ80F91 MCU Product Specification (PS0192) for more details
about controlling on-chip Flash memory and SRAM.
UM014220-0508
eZ80 Development Kit
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