EZ80F910200ZCO Zilog, EZ80F910200ZCO Datasheet - Page 27

• Manufacturer Part Number: EZ80F910200ZCO
• Description: KIT DEV FOR EZ80F91 W/C-COMPILER
• Manufacturer: Zilog

Specifications of EZ80F910200ZCO

• Processor To Be Evaluated: eZ80F91
• Interface Type: Ethernet
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3154; EZ80F910200ZCO

UM014220-0508
Table 7. CPU Bus Connector J8* (Continued)
Signal
BUSACK
NMI
D[0:7]
CS[0:3]
MREQ
WR
INSTRD
BUSREQ
PHI
Note: *All of the signals except BUSACK and INSTRD are driven by low-voltage CMOS technology
(LVC) drivers.
I/O Functionality
The eZ80Acclaim!
functions are memory-mapped with an address decoder based on the
Generic Array Logic GAL22lV10D (U15) device manufactured by Lat-
tice Semiconductor, and a bidirectional latch (U16). Additionally, U15 is
used to decode addresses for access to the 7 x 5 LED matrix.
Table 8
tions. The register at address
LED Anode register functions. The register at address
the register functions for the LED cathode, modem reset, and user triggers.
Address
Pin #
37
39
43–50
53–56
57
34
36
38
40
lists the addresses of registers that allow access to the above func-
800002h
Function
CPU Bus Acknowledge Signal
Nonmaskable Interrupt
Data Bus
Chip Selects
Memory Request
Write Signal
Instruction Fetch
CPU Bus Request signal
Clock output of the CPU
contains GPIO data.
®
Development Kit provides I/O functionality. These
800000h
controls GPIO Output Control and
eZ80F91 Development Kit
eZ80 Development Kit
800001h
User Manual
Direction
OUT
IN
IN/OUT
OUT
OUT
OUT
OUT
controls
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