EZ80F910200ZCO Zilog, EZ80F910200ZCO Datasheet - Page 56

• Manufacturer Part Number: EZ80F910200ZCO
• Description: KIT DEV FOR EZ80F91 W/C-COMPILER
• Manufacturer: Zilog

Specifications of EZ80F910200ZCO

• Processor To Be Evaluated: eZ80F91
• Interface Type: Ethernet
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3154; EZ80F910200ZCO

//Init_IRDA
// Make sure to first set PD2 as a port bit, an output and set it Low.
PD_ALT1 &= 0xFC;
PD_ALT2 |= 0x03;
UART_LCTL0= 0x80;
BRG_DLRL0=0x2F;
BRG_DLRH0=0x00;
UART_LCTL0=0x00;
UART_FCTL0=0xC7;
UART_LCTL0=0x03;
IR_CTL = 0x03;
//IRDA_Xmit
IR_CTL = 0x01;
Putchar(0xb0);
Flash Loader Utility
Mounting the Module
UM014220-0508
The Flash Loader utility integrated within ZDS II provides a convenient
way to program on-chip Flash memory. Refer to Zilog Developer Studio
II—eZ80Acclaim!
The eZ80F91 Module features two 60-pin connectors. However, the
eZ80Acclaim!
ule. When mounting the eZ80F91 Module onto the eZ80Acclaim! Devel-
opment Kit, check its orientation to the platform to ensure a correct fit.
Observe the underside of the module to note that pin 60 of the JP2 con-
nector is removed and that its corresponding socket on the eZ80Acclaim!
Development Kit is plugged.
Pin 60 of the eZ80F91 Module’s JP1 connector must align with the pin 50
socket on the eZ80Acclaim! Development Kit’s JP1 connector; pin 60 of
the eZ80F91 Module’s JP2 connector must align with pin 50 of the
// PD0 = uart0tx, PD1 = uart0_rx
// Enable alternate function
// Select dlab to access baud rate generator
// Baud rate Masterclock/(16*baudrate)
// High byte of baud rate
// Disable dlab
// Clear tx fifo, enable fifo
// 8bit, N, 1 stop
// enable IRDA Encode/decode and Receive
// enable bit.
//Disable receive
//Output a byte to the uart0 port.
®
Development Kit contains 50-pin sockets for this mod-
®
User Manual (UM0144) for more details.
eZ80F91 Development Kit
User Manual
eZ80F91 Module
51