EZ80F910200ZCO Zilog, EZ80F910200ZCO Datasheet - Page 70
EZ80F910200ZCO
Manufacturer Part Number
EZ80F910200ZCO
Description
KIT DEV FOR EZ80F91 W/C-COMPILER
Manufacturer
Zilog
Datasheet
1.EZ80F910200ZCO.pdf
(78 pages)
Specifications of EZ80F910200ZCO
Processor To Be Evaluated
eZ80F91
Interface Type
Ethernet
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3154
EZ80F910200ZCO
EZ80F910200ZCO
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Appendix A—General Array Logic
Equations
UM014220-0508
U10 Address Decoder
//`define idle
//`define state1
//`define state2
//`define state3
// FOR eZ80 Development Platform Rev B
// This PAL generates 4 memory chip selects
module f92_decod(
nCS_EX, //Enables Extension Module's Memory when Low
nFL_DIS,//When Low, Module Flash is disabled (nDIS_FL=0),
nCS0,
A7,
A6,
A5,
A4,
A3,
A2,
A1,
A0,
This appendix shows the equations for disabling the Ethernet signals pro-
vided by the U10 and U15 General Array Logic (GAL) devices.
//When High, nDIS_FL depends upon state of
//nmemenX
//A23
//A22
//A21
//A20
//A19
//A18
//A17
//A16
2'b00
2'b01
2'b11
2'b10
Appendix A—General Array Logic Equations
eZ80F91 Development Kit
User Manual
65
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