EVALPM6680 STMicroelectronics, EVALPM6680 Datasheet - Page 43

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EVALPM6680

Manufacturer Part Number
EVALPM6680
Description
BOARD EVALUATION FOR PM6680
Manufacturer
STMicroelectronics
Datasheet

Specifications of EVALPM6680

Mfg Application Notes
PM6680 Eval Kit, AN2566 App Note
Main Purpose
DC/DC, Step Down with LDO
Outputs And Type
3, Non-Isolated
Power - Output
13.25W
Voltage - Output
1.05V, 1.5V, 5V
Current - Output
5A, 5A, 100mA
Voltage - Input
6 ~ 28V
Regulator Topology
Buck
Frequency - Switching
200kHz, 300kHz
Board Type
Fully Populated
Utilized Ic / Part
PM6680
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6241

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EVALPM6680
Manufacturer:
ST
0
Part Number:
EVALPM6680A
Manufacturer:
ST
0
PM6680
Equation 39
OUT2:
Equation 40
Equation 41
(Let's assume Tmax = 75 °C in R
5.
6.
7.
8.
9.
(Let's assume the maximum temperature Tmax = 75 °C in RDSon calculation)
Input capacitor
Maximum input capacitor RMS current is about 2.8 A. Then I
We put three 10 uF ceramic capacitors with Irms = 1.5 A.
Synchronous rectifier
OUT1: Shottky diode STPS1L30M
OUT2: Shottky diode STPS1L30M
Integrator loop
(Refer to
OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required.
C
C = 5.6 nF; R= 36 kΩ; R1 = 3 kΩ
OUT2: The ripple is smaller than 40 mV, then the virtual ESR network is required.
C
C = 5.6 nF; R = 22 kΩ; R1 = 3.3 kΩ
Output feedback divider
(Refer to
OUT1: R1 = 10 kΩ; R2 = 6.8 kΩ
OUT2: R1 = 11 kΩ; R2 = 1.8 kΩ
Layout guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is
possible to refer to the PM6680 demoboard for a complete layout example.
For good PC board layout follows these guidelines:
Place on the top side all the power components (inductors, input and output capacitors,
MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve
a layer to PGND plan. The PGND plan is the same for both the switching sections.
AC current paths layout is very critical (see
minimize their length. Trace the LS MOSFET connection to PGND plan as short as
INT
INT
= 1 nF; C
= 1 nF; C
Figure 37
Figure 30 on page 24
filt
filt
= 110pF; R
= 47 pF; R
)
I
Lvalley
R
R
CSENSE
CSENSE
(min)
INT
INT
DSon
)
=
=1 kΩ
= 1 kΩ
I
100
LOAD
100
calculation)
. 4
4
12
2 .
µ
µ
A
(max)
A
A
A
16
16
Figure 41 on page 44
.
.
25
25
m
m
I
L
(min)
2
670
680
=
4
2 .
CinRMS
A
). The first priority is to
Device description
> 2.8 A.
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