COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 53
COP8SA-DM
Manufacturer Part Number
COP8SA-DM
Description
MODULE DEBUGGING FOR COP8SA
Manufacturer
National Semiconductor
Datasheet
1.DM-COP820D.pdf
(254 pages)
Specifications of COP8SA-DM
Module/board Type
Debugger Module
For Use With/related Products
Cop 8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*COP8SA-DM
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The device is initialized when the RESET pin is pulled low or the On-chip Power-On
Reset is enabled.
The following occurs upon initialization:
Port L: TRISTATE
Port C: TRISTATE
Port G: TRISTATE
Port F: TRISTATE
Port D: HIGH
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
T1CNTRL: CLEARED
Accumulator, Timer 1:
WKEN, WKEDG: CLEARED
WKPND: RANDOM
SP (Stack Pointer):
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RANDOM after RESET with crystal clock option (power already applied)
UNAFFECTED after RESET with R/C clock option (power already applied)
RANDOM after RESET at power-on
Initialized to RAM address 02F Hex (devices with 64 bytes of RAM), or ini-
tialized to RAM address 06F Hex (devices with 128 bytes of RAM).
EXTERNAL
ON-CHIP
POWER-ON
RESET
Figure 2-7 Reset Logic
ECON
Bit 6
COP8SAx7 MICROCONTROLLER
INTERNAL
RESET
2-15
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