COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 55
COP8SA-DM
Manufacturer Part Number
COP8SA-DM
Description
MODULE DEBUGGING FOR COP8SA
Manufacturer
National Semiconductor
Datasheet
1.DM-COP820D.pdf
(254 pages)
Specifications of COP8SA-DM
Module/board Type
Debugger Module
For Use With/related Products
Cop 8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*COP8SA-DM
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at least VCC (min). The desired response is shown in Figure 2-9.
On-chip Power-On Reset
The on-chip reset circuit is selected by a bit in the ECON register. When enabled, the
device generates an internal reset as V
reset circuitry is able to detect both fast and slow rise times on V
between 10 ns and 50 ms).
Under no circumstances should the RESET pin be allowed to float. If the on-chip Power-
On Reset feature is being used, RESET pin should be connected directly to V
output of the power-on reset detector will always preset the Idle timer to 0FFF(4096 tc).
At this time, the internal reset will be generated.
If the Power-On Reset feature is enabled, the internal reset will not be turned off until
the Idle timer underflows. The internal reset will perform the same functions as external
reset. The user is responsible for ensuring that V
operating frequency within the 4096 tc. After the underflow, the logic is designed such
that no additional internal resets occur as long as V
The contents of data registers and RAM are unknown following the on-chip reset.
V
CC
Figure 2-9 Dddesired Reset Response Time
V
(min)
IL
(R)
Volts
CC
rises to a voltage level above 2.0V. The on-chip
V
t
CC
CC
CC
COP8SAx7 MICROCONTROLLER
is at the minimum level for the
remains above 2.0V.
External
RESET
Timer
CC
(V
CC
rise time
CC
. The
2-17
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