HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 140

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HW-SPAR3E-SK-US-G

Manufacturer Part Number
HW-SPAR3E-SK-US-G
Description
KIT STARTER SPARTAN-3E
Manufacturer
Xilinx Inc
Datasheets

Specifications of HW-SPAR3E-SK-US-G

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1507
DC and Switching Characteristics
Clock Buffer/Multiplexer Switching Characteristics
Table 101: Clock Distribution Switching Characteristics
140
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1
inputs. Same as BUFGCE enable CE-input
Frequency of signals distributed on global buffers (all sides)
Description
www.xilinx.com
Symbol
F
T
T
BUFG
GIO
GSI
1.46
0.55
333
Speed Grade
-5
DS312-3 (v3.8) August 26, 2009
Maximum
Product Specification
1.46
0.63
311
-4
Units
MHz
ns
ns
R

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