HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 202
![no-image](/images/no-image-200.jpg)
HW-SPAR3E-SK-US-G
Manufacturer Part Number
HW-SPAR3E-SK-US-G
Description
KIT STARTER SPARTAN-3E
Manufacturer
Xilinx Inc
Specifications of HW-SPAR3E-SK-US-G
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1507
- XC3S100E-4VQG100C PDF datasheet
- HW-USB-G_PRODUCT_CHANGE PDF datasheet #2
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Pinout Descriptions
FT256 Footprint
202
28
2
6
M
A
B
C
D
E
G
H
K
N
P
R
F
J
L
T
CONFIG: Dedicated
configuration pins
GND: Ground
Migration Difference: For
flexible package migration,
use these pins as inputs.
VCCAUX
VCCAUX
VREF_3
INPUT
INPUT
L01P_3
L02P_3
L05P_3
L05N_3
L12P_3
L12N_3
L16P_3
L16N_3
L18N_3
L19N_3
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
VCCO_3
VCCO_3
VREF_3
INPUT
INPUT
LHCLK4
VREF_3
INPUT
VREF_3
INPUT
L01N_3
L02N_3
L07N_3
L10P_3
L13P_3
L14N_3
L18P_3
L19P_3
TRDY2
GND
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2
PROG_B
INPUT
HSWAP
LHCLK2
LHCLK5
INPUT
INPUT
INPUT
INPUT
L19N_0
L19P_0
L03P_3
L04P_3
L07P_3
L09P_3
L10N_3
L13N_3
L14P_3
L01P_2
L02N_2
L02P_2
CSO_B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
3
VCCINT
VCCINT
VREF_0
VREF_3
LHCLK3
LHCLK7
INPUT
VREF_2
L17N_0
L18N_0
L03N_3
L04N_3
L06N_3
L09N_3
L11N_3
L17N_3
L01N_2
L17P_3
L04P_2
INIT_B
IRDY2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
4
VCCINT
VCCINT
VCCO_0
VCCO_2
Figure 86: FT256 Package Footprint (top view)
LHCLK0
LHCLK6
INPUT
INPUT
L15N_3
L03N_2
L04N_2
L17P_0
L18P_0
L16P_0
L06P_3
L08P_3
L11P_3
L15P_3
L03P_2
CSI_B
DOUT
BUSY
MOSI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
5
VCCAUX
VCCO_3
VCCO_3
VCCAUX
LHCLK1
( )
INPUT
INPUT
INPUT
L15P_0
L15N_0
L16N_0
L08N_3
L05P_2
L05N_2
L06N_2
L06P_2
16
18
GND
GND
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
VCCO_0
VCCO_2
VREF_0
INPUT
INPUT
INPUT
VREF_2
L13P_0
L13N_0
L14N_0
L14P_0
L07P_2
L07N_2
L08P_2
L08N_2
GND
GND
GND
GND
JTAG: Dedicated JTAG port
pins
VCCO: Output voltage supply
for bank
Unconnected pins on
XC3S250E
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
www.xilinx.com
Bank 2
INPUT
INPUT
GCLK10
GCLK11
GCLK13
GCLK12
GCLK14
GCLK15
L10P_0
L10N_0
L11P_0
L11N_0
L12P_0
L12N_0
L09N_2
L09P_2
L10P_2
L10N_2
GCLK8
GCLK9
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D6
D7
D4
D3
D5
8
Bank 0
RDWR_B
INPUT
VREF_0
INPUT
L09N_0
L07N_0
L08N_0
L13N_2
L12N_2
L11N_2
INPUT
GCLK7
L08P_0
GCLK4
GCLK5
L13P_2
GCLK3
L12P_2
GCLK2
GCLK1
L11P_2
GCLK0
GND
GND
GND
GND
GND
DIN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M0
D0
D1
D2
M2
9
VCCO_0
VCCO_2
VREF_2
INPUT
INPUT
L06N_0
L15N_2
L09P_0
GCLK6
L07P_0
L06P_0
L15P_2
L14P_2
L14N_2
GND
GND
GND
GND
10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1
VCCAUX
VCCAUX
VCCO_1
RHCLK7
VCCO_1
VREF_0
INPUT
INPUT
INPUT
L05N_0
L05P_0
L04P_0
L04N_0
L12N_1
L17N_2
L17P_2
L16N_2
L16P_2
GND
GND
A22
A23
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
3
VCCINT
VCCINT
VCCO_0
RHCLK6
VCCO_2
INPUT
INPUT
INPUT
INPUT
INPUT
L02N_0
L02P_0
L16N_1
L12P_1
L07N_1
L05P_1
L18N_2
L18P_2
A11
A20
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A21
A4
8
8
VCCINT
VCCINT
RHCLK3
VREF_0
INPUT
INPUT
VREF_1
INPUT
VREF_2
L03N_0
L03P_0
L17P_1
L16P_1
L14P_1
L10N_1
L07P_1
L05N_1
L19N_2
L19P_2
TRDY1
VS1
VS2
13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A12
I/O
I/O
I/O
A18
I/O
A19
A
7
VCCINT: Internal core supply
voltage (+1.2V)
VCCAUX: Auxiliary supply
voltage (+2.5V)
DS312-4 (v3.8) August 26, 2009
RHCLK5
RHCLK2
INPUT
VREF_1
INPUT
INPUT
L01N_0
L18N_1
L14N_1
L11N_1
L20N_2
L01P_0
L15P_1
L10P_1
L08N_1
L06P_1
L03P_1
L20P_2
TDO
CCLK
LDC0
VS0
A17
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A0
A5
A8
VCCO_1
VCCO_1
RHCLK4
VREF_1
DONE
L19N_1
L18P_1
L15N_1
L13P_1
L11P_1
L08P_1
L06N_1
L03N_1
L02N_1
L01N_1
IRDY1
GND
TCK
TMS
LDC2
HDC
A13
A15
15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Product Specification
A2
A
6
DS312-4_05_101805
VCCAUX
VCCAUX
RHCLK1
RHCLK0
INPUT
INPUT
VREF_1
INPUT
VREF_1
L19P_1
L17N_1
L13N_1
L09N_1
L09P_1
L04N_1
L04P_1
L02P_1
L01P_1
GND
GND
LDC1
A10
A14
A16
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A1
A9
R
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