HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 124

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Chapter 15: Expansion Connectors
UCF Location Constraints
124
Header J4
The J4 header, shown in
uses a 6-pin header consisting of 0.1-inch centered stake pins. Four FPGA pins connect to
the J4 header, FX2_IO<12:9>. These four signals are also shared with the Hirose FX2
connector. The board supplies 3.3V to the accessory board mounted in the J4 socket on the
bottom pin.
Figure 15-11
including the I/O pin assignment and the I/O standard used. These header connections
are shared with the FX2 connector, as shown in
# ==== 6-pin header J1 ====
# These four connections are shared with the FX2 connector
#NET
#NET
#NET
#NET
# ==== 6-pin header J2 ====
# These four connections are shared with the FX2 connector
#NET
#NET
#NET
#NET
# ==== 6-pin header J4 ====
# These four connections are shared with the FX2 connector
#NET
#NET
#NET
#NET
"J1<0>"
"J1<1>"
"J1<2>"
"J1<3>"
"J2<0>"
"J2<1>"
"J2<2>"
"J2<3>"
"J4<0>"
"J4<1>"
"J4<2>"
"J4<3>"
Figure 15-11: UCF Location Constraints for Accessory Headers
Figure 15-10: FPGA Connections to the J4 Accessory Header
provides the User Constraint File (UCF) constraints for accessory headers,
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC
= "B4" |
= "A4" |
= "D5" |
= "C5" |
= "A6" |
= "B6" |
= "E7" |
= "F7" |
= "D7" |
= "C7" |
= "F8" |
= "E8" |
Figure
www.xilinx.com
Spartan-3E FPGA
15-10, is located immediately to the left of the J1 header. It
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
(D7)
(C7)
(E8)
(F8)
Spartan-3E FPGA Starter Kit Board User Guide
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
= LVTTL
FX2_IO10
FX2_IO11
FX2_IO12
FX2_IO9
Figure 15-7, page
GND
3.3V
UG230_c12_09_022406
|
|
|
|
|
|
|
|
|
|
|
|
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
J4
UG230 (v1.2) January 20, 2011
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
= SLOW
122.
|
|
|
|
|
|
|
|
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
= 6 ;
R