HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 45
![KIT STARTER SPARTAN-3E](/photos/24/12/241249/4579285_sml.jpg)
HW-SPAR3E-SK-UK-G
Manufacturer Part Number
HW-SPAR3E-SK-UK-G
Description
KIT STARTER SPARTAN-3E
Manufacturer
Xilinx Inc
Specifications of HW-SPAR3E-SK-UK-G
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Development Tool Type
Hardware / Software - Starter Kit
Mcu Supported Families
Spartan-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
HW-SPAR3E-SK-US-UK-G
HW-SPAR3E-SK-US-UK-G
HW-SPAR3E-SK-US-UK-G
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UCF Location Constraints
LCD Controller
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
1
2
00
40
1
Memory Map
01
41
2
R
02
42
3
DD RAM
Figure 5-3: DD RAM Hexadecimal Addresses (No Display Shifting)
03
43
4
If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA
application has full simultaneous read/write access to both the LCD and the StrataFlash
memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> data
lines.
Figure 5-2
assignment and the I/O standard used.
The 2 x 16 character LCD has an internal Sitronix
functionally equivalent with the following devices.
•
•
•
The controller has three internal memory regions, each with a specific purpose. The
display must be initialized before accessing any of these memory regions.
The Display Data RAM (DD RAM) stores the character code to be displayed on the screen.
Most applications interact primarily with DD RAM. The character code stored in a DD
RAM location references a specific character bitmap stored either in the predefined
ROM
Figure
upper line of characters is stored between addresses 0x00 and 0x0F. The second line of
characters is stored between addresses 0x40 and 0x4F.
Samsung S6A0069X or KS0066U
Hitachi HD44780
SMOS SED1278
04
44
NET
NET
NET
# The LCD four-bit data interface is shared with the StrataFlash.
NET
NET
NET
NET
5
character set or in the user-defined
5-3shows the default address for the 32 character locations on the display. The
"LCD_E"
"LCD_RS"
"LCD_RW"
"SF_D<8>"
"SF_D<9>"
"SF_D<10>"
"SF_D<11>"
05
45
provides the UCF constraints for the Character LCD, including the I/O pin
6
Character Display Addresses
Figure 5-2: UCF Location Constraints for the Character LCD
06
46
7
LOC
LOC
LOC
LOC
LOC
LOC
LOC
07
47
8
= "M18" |
= "L18" |
= "L17" |
= "R15" |
= "R16" |
= "P17" |
= "M15" |
www.xilinx.com
08
48
9
10
09
49
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
0A
4A
11
CG RAM
0B
4B
12
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
ST7066U
0C
4C
13
character set.
0D
4D
14
graphics controller that is
DRIVE
DRIVE
DRIVE
UCF Location Constraints
DRIVE
DRIVE
DRIVE
DRIVE
0E
4E
15
= 4 |
= 4 |
= 4 |
0F
4F
16
= 4 |
= 4 |
= 4 |
= 4 |
10
50
17
SLEW
SLEW
SLEW
Undisplayed
SLEW
SLEW
SLEW
SLEW
Addresses
…
…
…
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
= SLOW ;
CG
27
67
40
45
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