HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 70

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Chapter 9: Digital to Analog Converter (DAC)
70
Interface Signals
Disable Other Devices on the SPI Bus to Avoid Contention
Table 9-1
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 9-1: DAC Interface Signals
The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.
The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the DAC to avoid bus contention.
Table 9-2
Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared
with the SPI_MISO signal.
SPI_MOSI
DAC_CS
SPI_SCK
DAC_CLR
SPI_MISO
Signal
(N10)
Spartan-3E FPGA
lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
provides the signals and logic values required to disable the other devices.
Figure 9-2: Digital-to-Analog Connection Schematics
FPGA Pin
N10
U16
(U16)
N8
T4
P8
(N8)
(T4)
(P8)
3.3V
2.5V
SPI_MISO
SPI_MOSI
DAC_CLR
SPI_SCK
DAC_CS
www.xilinx.com
FPGADAC
FPGADAC
FPGADAC
FPGADAC
FPGADAC
Direction
REF A
REF B
REF C
REF D
LTC 2624 DAC
SDI
CS/LD
SCK
CLR
SPI Control Interface
Spartan-3E FPGA Starter Kit Board User Guide
Serial data: Master Output, Slave Input
Active-Low chip-select. Digital-to-analog
conversion starts when signal returns High.
Clock
Asynchronous, active-Low reset input
Serial data: Master Input, Slave Output
12
12
12
12
DAC A
DAC B
DAC C
DAC D
UG230 (v1.2) January 20, 2011
Description
SDO
VOUTA
VOUTB
VOUTC
VOUTD
Header J5
UG230_c9_02_021806
A
B
C
D
GND
VCC
(3.3V)
R