HW-SPAR3E-SK-UK-G Xilinx Inc, HW-SPAR3E-SK-UK-G Datasheet - Page 23

• Manufacturer Part Number: HW-SPAR3E-SK-UK-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-UK-G

• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Development Tool Type: Hardware / Software - Starter Kit
• Mcu Supported Families: Spartan-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: HW-SPAR3E-SK-US-UK-G; HW-SPAR3E-SK-US-UK-G

Related Resources
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
Clock Period Constraints
R
The Xilinx ISE
Set the clock PERIOD constraint as appropriate. An example constraint appears in
Figure 3-3
50 MHz, which equates to a 20 ns period. The output duty cycle from the oscillator ranges
between 40% to 60%.
•
Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
NET
NET
NET
# Define clock period for 50 MHz oscillator
NET
"CLK_50MHZ"
"CLK_SMA"
"CLK_AUX"
"CLK_50MHZ"
for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is
®
Figure 3-2: UCF Location Constraints for Clock Sources
development software uses timing-driven logic placement and routing.
Figure 3-3: UCF Clock PERIOD Constraint
LOC
LOC
LOC
PERIOD
www.xilinx.com
= "C9"
= "A10" |
= "B8"
= 20.0ns
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
HIGH
40%;
= LVCMOS33 ;
= LVCMOS33 ;
= LVCMOS33 ;
Related Resources
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