MAX17009GTL+ Maxim Integrated Products, MAX17009GTL+ Datasheet - Page 23

• Manufacturer Part Number: MAX17009GTL+
• Description: IC CTLR VIDEO SERIAL DUAL 40TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17009GTL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The maximum allowable AC droop is limited by the rec-
ommended integrator correction range of ±100mV and
on the DC droop:
The MAX17009 controller includes independent differ-
ential, remote-sense inputs for each CPU core to elimi-
nate the effects of voltage drops along the PC board
(PCB) traces and through the processor’s power pins.
The feedback-sense (FBDC_) input connects to the
voltage-positioning resistor (R
sense (GNDS_) input connects to an amplifier that
adds an offset directly to the target voltage, effectively
adjusting the output voltage to counteract the voltage
drop in the ground path. Connect the feedback-sense
(FBDC_) voltage-positioning resistor (R
ground-sense (GNDS_) input directly to the respective
CPU core’s remote-sense outputs as shown in Figure 2.
GNDS2 has a dual function. At power-on, the voltage
level on GNDS2 configures the MAX17009 as two inde-
pendent switching regulators, or one higher current
two-phase regulator. Keep GNDS2 low during power-
up to configure the MAX17009 in separate mode.
Connect GNDS2 to a voltage above 0.8V (typ) for com-
bined-mode operation. In the AMD mobile system, this
is automatically done by the CPU that is plugged into
the socket that pulls GNDS2 to the V
The MAX17009 checks the GNDS2 level at the time
when the internal REFOK signal goes high, and latches
the operating mode information (separate or combined
mode). This latch is cleared by cycling the SHDN pin.
An internal integrator amplifier forces the DC average
of the FBDC_ voltage to equal the target voltage. This
transconductance amplifier integrates the feedback
voltage and provides a fine adjustment to the regulation
voltage (Figure 3), allowing accurate DC output-voltage
regulation regardless of the output-ripple voltage. The
integrator amplifier has the ability to shift the output
voltage by ±100mV (min).
The MAX17009 disables the integrator by connecting
the amplifier inputs together at the beginning of all VID
transitions done in pulse-skipping mode. The integrator
remains disabled until 20µs after the transition is com-
pleted (the internal target settles), and the output is in
regulation (edge detected on the error comparator).
When voltage positioning is disabled (R
the AC droop setting must be less than the ±100mV
R
FBAC
−
R
FBDC
______________________________________________________________________________________
≤
1 03
.
mSI
Differential Remote Sense
LOAD MAX SENSE
AMD Mobile Serial VID Dual-Phase
FBDC_
100
Integrator Amplifier
DDIO
(
mV
). The ground-
)
FBDC_
voltage level.
R
FBDC_
= 0Ω),
), and
Fixed-Frequency Controller
minimum adjustment range of the integrator amplifier to
guarantee proper DC output-voltage accuracy. See the
Steady State Voltage-Positioning Amplifiers (DC Droop)
and the Transient Voltage-Positioning Amplifiers (AC
Droop) sections.
The MAX17009 supports the 2-wire, write only, serial-
interface bus as defined by the AMD Serial VID
Interface Specification. The serial interface is similar to
the high-speed 3.4MHz I
mode sequence. The bus consists of a clock line (SVC)
and a data line (SVD). The CPU is the bus master, and
the MAX17009 is the slave. The MAX17009 serial inter-
face works from 100kHz to 3.4MHz. In the AMD mobile
application, the bus runs at 3.4MHz.
The serial interface is active only after PGD_IN goes
high in the startup sequence. The CPU sets the VID
voltage of the three internal DACs and the PSI_L bit
through the serial interface.
During the startup sequence, the SVC and SVD inputs
serve an alternate function to set the 2-bit boot VID for
all three DACs while PWRGD is low. In debug mode,
the SVC and SVD inputs function in the 2-bit VID mode
when PGD_IN is low, and in the serial-interface mode
when PGD_IN is high.
The nominal no-load output voltage (V
each SMPS is defined by the selected voltage refer-
ence (VID DAC) plus the remote ground-sense adjust-
ment (V
defined in the following equation:
where V
DAC, V
and V
OPTION pin, when the PSI_L is set high.
The nominal output voltage (V
is defined by the selected voltage reference (VID DAC)
plus the remote ground-sense adjustment (V
defined in the following equation:
where V
NBV_BUF DAC, and V
correction voltage. The offset voltage (V
applied to NBV_BUF.
V
OFFSET
V
TARGET
GNDS
TARGET
DAC
GNDS
DAC_
2-Wire Serial Interface (SVC, SVD)
Nominal Output-Voltage Selection
is the selected VID voltage of the SMPS
is the ground-sense correction voltage,
) and the offset voltage (V
is the +12.5mV offset enabled by the
=
is the selected VID voltage of the
=
V
FBDC
V
NBV BUF
_
GNDS_NB_
=
2
V
C bus, but without the master
DAC
NBV_BUF Output Voltage
=
TARGET
V
+
DAC
SMPS Output Voltage
V
GNDS
is the ground-sense
+
) for the NBV_BUF
V
GNDS NB
+
OFFSET
V
TARGET_
OFFSET
OFFSET
_
GNDS
) is not
) for
), as
) as
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