MAX17009GTL+ Maxim Integrated Products, MAX17009GTL+ Datasheet - Page 39

• Manufacturer Part Number: MAX17009GTL+
• Description: IC CTLR VIDEO SERIAL DUAL 40TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17009GTL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where N is the number of high-side MOSFETs used for
one regulator, and Q
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V
boost capacitance would be:
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
The MAX17009 is a receive-only device. The 2-wire ser-
ial bus (pins SVC and SVD) is designed to attach on a
low-voltage, I
tion, the CPU directly drives the bus at a speed of
3.4MHz. The CPU has a push-pull output driving to the
V
required during the initial power-up sequence before
the CPU’s push-pull drivers are active. Refer to AMD for
specific implementation.
When not used in the specific AMD application, the ser-
ial interface can be driven to as high as 2.5V, and oper-
ate at the lower speeds (100kHz, 400kHz, or 1.7MHz).
At lower clock speeds, external pullup resistors can be
used for open-drain outputs. Connect both SVC and
SVD lines to V
Calculate the required value of the pullup resistors
using:
where t
of the clock period. C
the bus.
Figure 10. SVI Bus START, STOP, and Data Change Conditions
DDIO
GS
SVD
SVC
= 5V). Using the above equation, the required
voltage level. External pullup resistors may be
R
SVI Applications Information
is the rise time, and should be less than 10%
CONDITION
2
C-like bus. In the AMD mobile applica-
DDIO
START
C
S
BST
I
______________________________________________________________________________________
2
R
C-Bus-Compatible Interface
PULLUP
through individual pullup resistors.
=
GATE
2 24
BUS
200
×
is the gate charge specified
mV
is the total capacitance on
nC
≤
C
BUS
=
t
R
AMD Mobile Serial VID Dual-Phase
0 24
.
DATA VALID
DATA LINE
STABLE
μ
F
ALLOWED
CHANGE
OF DATA
Fixed-Frequency Controller
The MAX17009 is compatible with the standard SVI inter-
face protocol as defined in the following subsections.
The SVI bus is not busy when both data and clock lines
remain HIGH. Data transfers can be initiated only when
the bus is not busy.
Starting from an idle bus state (both SVC and SVD are
high), a HIGH to LOW transition of the data (SVD) line
while the clock (SVC) is HIGH determines a START
condition. All commands must be preceded by a
START condition.
A LOW to HIGH transition of the SDA line while the
clock (SVC) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
Figure 10 shows the SVI bus START, STOP, and data
change conditions
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (110xxxx) for the MAX17009. Since the
MAX17009 is a write-only device, the eighth bit of the
slave address is zero. The MAX17009 monitors the bus
for its corresponding slave address continuously. It
generates an acknowledge bit if the slave address was
true and it is not in a programming mode.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The
data on the line must be changed during the LOW peri-
od of the clock signal. There is one clock pulse per bit
of data.
Start Data Transfer (S)
Stop Data Transfer (P)
CONDITION
STOP
P
SVD Data Valid
Slave Address
Bus Not Busy
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