MAX17009GTL+ Maxim Integrated Products, MAX17009GTL+ Datasheet - Page 25

• Manufacturer Part Number: MAX17009GTL+
• Description: IC CTLR VIDEO SERIAL DUAL 40TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17009GTL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inside the MAX17009 are three 7-bit digital-to-analog
converters (DACs). Each DAC can be individually pro-
grammed to different voltage levels through the serial-
interface bus. The DAC sets the target for the output
voltage for the SMPSs and the NB buffer output
(NBV_BUF). The available DAC codes and resulting
output voltages are compatible with the AMD SVI
(Table 4) specifications
On startup, the MAX17009 slews the target for all three
DACs from ground to the boot voltage set by the SVC
and SVD pin voltage levels. While the output is still below
regulation, the SVC and SVD levels can be changed,
and the MAX17009 sets the DACs to the new boot volt-
age. Once the programmed boot voltage is reached and
PWRGD goes high, the MAX17009 stores the boot VID.
Changes in the SVC and SVD settings do not change the
output voltage once the boot VID is stored. When
PGD_IN goes high, the MAX17009 exits boot mode, and
the three DACs can be independently set to any voltage
in the VID table through the serial interface.
If PGD_IN goes from high to low anytime after the boot
VID is stored, the MAX17009 sets all three DACs back
to the voltage of the stored boot VID.
When in debug mode (PRO = OPEN), the MAX17009
uses a different boot-voltage code set. Keeping
PGD_IN low allows the SVC and SVD inputs to set the
three DACs to different voltages in the boot-voltage
code table. When PGD_IN is subsequently set high, the
three DACs can be independently set to any voltage in
the VID table serial interface. Table 3 shows the boot-
voltage code table.
Table 3. Boot-Voltage Code Table
A +12.5mV offset can be added to both SMPS DAC
voltages for applications that include DC droop. The
offset is applied only after the MAX17009 exits boot
mode (PGD_IN going from low to high), and the
MAX17009 enters the serial-interface mode. The offset
is disabled when the PSI_L bit is set, saving more
power when the load is light.
SVC
0
0
1
1
SVD
0
1
0
1
(PRO = V
BOOT VOLTAGE
______________________________________________________________________________________
(V
BOOT
C C
1.1
1.0
0.9
0.8
O R G N D )
)
AMD Mobile Serial VID Dual-Phase
BOOT VOLTAGE
(PRO = OPEN)
Boot Voltage
(V
BOOT
7-Bit DAC
1.4
1.2
1.0
0.8
Offset
)
Fixed-Frequency Controller
The OPTION pin setting enables or disables the
+12.5mV offset. Connect OPTION to REF or GND to
enable the offset. Keep OPTION open or connected to
V
Phase Repeat ( OPTION) section.
The MAX17009 performs positive voltage transitions in a
controlled manner, automatically minimizing input surge
currents. This feature allows the circuit designer to
achieve nearly ideal transitions, guaranteeing just-in-time
arrival at the new output voltage level with the lowest
possible peak currents for a given output capacitance.
The slew rate (set by resistor R
enough to ensure that 35.7kΩ and 357kΩ for corre-
sponding slew rates between 25mV/µs to 2.5mV/µs,
respectively, for the SMPSs.
At the beginning of an output-voltage transition, the
MAX17009 blanks both PWRGD comparator thresh-
olds, preventing the PWRGD open-drain output from
changing states during the transition. At the end of an
upward VID transition, the controller enables both
PWRGD thresholds approximately 20µs after the slew-
rate controller reaches the target output voltage. At the
end of a downward VID transition, the upper PWRGD
threshold is enabled only after the output reaches the
lower VID code setting.
The MAX17009 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an internal
capacitor and current source programmed by R
transition the output voltage. The total transition time
depends on R
accuracy of the slew-rate controller (C
The slew rate is not dependent on the total output
capacitance, as long as the surge current is less than
the current limit set by ILIM. For all dynamic positive VID
transitions, the transition time (t
where dV
slew rate, V
is the new target voltage. See the TIME Slew-Rate
Accuracy row in the Electrical Characteristics table for
slew-rate limits.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. The average
inductor current per phase required to make an output-
voltage transition is:
CC
to disable the offset. See the Offset and Transient-
TARGET
OLD
Output-Voltage Transition Timing
TIME
t
is the original output voltage, and V
TRAN
/dt = 6.25mV/µs x 143kΩ / R
, the voltage difference, and the
SMPS Output-Voltage Transition
=
(
dV
V
NEW
TARGET
TRAN
−
TIME
V
OLD
/
) is given by:
dt
) must be set fast
)
SLEW
accuracy).
TIME
TIME
is the
NEW
25
to