MAX17009GTL+ Maxim Integrated Products, MAX17009GTL+ Datasheet - Page 31

• Manufacturer Part Number: MAX17009GTL+
• Description: IC CTLR VIDEO SERIAL DUAL 40TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX17009GTL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes:
1) The relationship between DC_IN and V
2) As the V
3) After SHDN is asserted, the MAX17009 samples
4) The MAX17009 asserts PWRGD. After PWRGD is
5) The processor holds the 2-bit boot VID for at least
6) The processor issues the set VID command through
7) The MAX17009 transitions the voltage planes to the
8) The chipset enforces a 1ms delay between PGD_IN
The MAX17009 features internal power-good fault com-
parators for each phase. The outputs of these individ-
ual power-good fault comparators are logically ORed to
drive the gate of the open-drain PWRGD output transis-
tor. Each phase’s power-good fault comparator has an
upper threshold of +200mV (typ) and a lower threshold
of -300mV (typ). PWRGD goes low if the output of either
phase exceeds its respective thresholds.
guaranteed. It is possible to have V
when DC_IN is not powered, and it is possible to
have DC_IN power-up before V
VDD_Plane_Strap becomes valid and SVC and SVD
are driven to the boot VID value by the processor.
The system guarantees that V
and SVC and SVD are driven to the boot VID value
for at least 10µs prior to SHDN being asserted to the
MAX17009.
and latches the VDD_Plane_Strap level at its
GNDS2 pin when REF reaches the REFOK thresh-
old, and ramps up the voltage-plane outputs to the
level indicated by the 2-bit boot VID. The boot VID
is stored in the MAX17009 for use when PGD_IN
deasserts. The MAX17009 soft-starts the output
rails to limit inrush current from the DC_IN rail.
asserted and all system-wide voltage planes and
free-running clocks are within specification, then
the system asserts PGD_IN.
10µs after PGD_IN is asserted.
SVI.
set VID. The set VID may be greater than, or less
than the boot VID voltage.
assertion and RESET_L deassertion.
DDIO
power rail comes within specification,
______________________________________________________________________________________
AMD Mobile Serial VID Dual-Phase
DDIO
DDIO
is in specification
powers up.
DDIO
DDIO
powered
PWRGD
is not
Fixed-Frequency Controller
PWRGD is forced low during the startup sequence up to
20µs after both SMPS internal DACs reach the boot VID.
The 2-bit boot VID is stored when PWRGD goes high
during the startup sequence. PWRGD is immediately
forced low when SHDN goes low.
PWRGD is blanked high impedance while either of the
internal SMPS DACs are slewing during a VID transition,
plus an additional 20µs after the DAC transition is com-
pleted. For downward VID transitions, the upper thresh-
old of the power-good fault comparators remains
blanked until the output reaches regulation again.
PWRGD goes low for a minimum of 20µs when PGD_IN
goes low, and stays low until 20µs after both SMPS
internal DACs reach the boot VID.
After the SMPS outputs reach the boot voltage, the
MAX17009 switches over to the serial-interface mode
when PGD_IN goes high. Anytime during normal opera-
tion, a high-to-low transition on PGD_IN causes the
MAX17009 to slew all three internal DACs back to the
stored boot VIDs. PWRGD goes low for a minimum of
20µs when PGD_IN goes low, and stays low until 20µs
after the SMPS outputs are within the PWRGD thresh-
olds. The SVC and SVD inputs are disabled during the
time that PGD_IN is low. The serial interface is reen-
abled when PGD_IN goes high again.
In debug mode (PRO = OPEN), the function of the SVC
and SVD inputs depend on the PGD_IN level. If
PGD_IN is low, the SVC and SVD inputs are used as 2-
bit inputs to set the three internal DAC voltages. See
Table 3. If PGD_IN is high, the MAX17009 switches
over to serial-interface mode. A high-to-low transition
on PGD_IN causes the MAX17009 to slew all three
internal DACs back to the stored boot VIDs and revert
to the 2-bit VID mode. See Figure 7.
PGD_IN
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