AD7782 Analog Devices, AD7782 Datasheet
AD7782
Specifications of AD7782
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AD7782 Summary of contents
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... V supplies, the power dissipation for the part is 3.9 mW. The AD7782 is available in a 16-lead TSSOP package. Another part in the AD778x family is the AD7783 similar to the AD7782 except it has two integrated current sources and only one differential input channel. AD7782 ...
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... V T(+) T(–) V T(+) V T(–) V – V T(+) T(– 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = GND; GND = XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications T AD7782B Unit 19.79 Hz nom 24 Bits min 16 Bits p-p 18 Bits p-p See Table I ± 10 ppm of FSR max ± 3 µV typ ± ...
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... V max ± 10 µA max ± typ Offset Binary 300 ms typ 2.7/3.6 V min/max 4.75/5.25 V min/max 1.5 mA max 1.7 mA max µA max 9 µA max 24 AD7782 Test Conditions GND, Typically –40 µ and –20 µ ...
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... AD7782 TIMING CHARACTERISTICS Limit at T Parameter (B Version) t 30.5176 1 t 50.54 ADC × ADC Slave Mode Timing t 100 6 t 100 7 Master Mode Timing ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7782 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... SCLK is Schmitt triggered (slave mode) making the interface suitable for opto- isolated applications. CS Chip Select Input active low logic input used to select the AD7782. When CS is low, the PLL 11 establishes lock and allows the AD7782 to initiate a conversion on the selected channel. When CS is high, the conversion is aborted, DOUT and SCLK are three-stated, the AD7782 enters standby mode and any conversion result in the output shift register is lost ...
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... The output rate of the AD7782 (f while the settling time equals: Normal-mode rejection is the major function of the digital filter on the AD7782. Simultaneous 50 Hz and 60 Hz rejection of better than achieved as notches are placed at both 50 Hz and 60 Hz. Figure 4 shows the filter rejection. ...
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... Figure 2 shows the timing diagram for interfacing to the AD7782 with CS used to decode the part. MASTER MODE (MODE = 0) In this mode, SCLK is provided by the AD7782. With CS low, SCLK becomes active when a conversion is complete and generates twenty four falling and rising edges. The DOUT/RDY pin, which is normally high, goes low to indicate that a conversion is complete ...
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... As a result, the AD7782 is more immune to noise inter- ference than a conventional high-resolution converter. However, because the resolution of the AD7782 is so high, and the noise levels from the AD7782 so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7782 should be designed such that the analog and digital sections are separated and confined to certain areas of the board ...
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... AD7782 SEATING OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Thin Shrink SO Plastic (TSSOP) (RU-16) 0.201 (5.10) 0.193 (4.90 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25 PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) ...
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