DSPIC30F2011-20I/P Microchip Technology, DSPIC30F2011-20I/P Datasheet - Page 93

• Manufacturer Part Number: DSPIC30F2011-20I/P
• Description: IC DSPIC MCU/DSP 12K 18DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2011-20I/P

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 18PDIP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 12
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2011-20IP

FIGURE 13-2:
13.3
The SS1 pin allows a Synchronous Slave mode. The
SPI must be configured in SPI Slave mode with SS1
pin control enabled (SSEN = 1). When the SS1 pin is
low, transmission and reception are enabled and the
SDOx pin is driven. When SS1 pin goes high, the
SDOx pin is no longer driven. Also, the SPI module is
resynchronized, and all counters/control circuitry are
reset. Therefore, when the SS1 pin is asserted low
again, transmission/reception will begin at the MSb
even if SS1 had been de-asserted in the middle of a
transmit/receive.
13.4
During Sleep mode, the SPI module is shut down. If the
CPU enters Sleep mode while an SPI transaction is in
progress, then the transmission and reception is
aborted.
The transmitter and receiver will stop in Sleep mode.
However, register contents are not affected by entering
or exiting Sleep mode.
© 2008 Microchip Technology Inc.
Slave Select Synchronization
SPI Operation During CPU Sleep
Mode
MSb
PROCESSOR 1
Serial Input Buffer
SPI MASTER/SLAVE CONNECTION
SPI Master
Shift Register
(SPI1BUF)
(SPI1SR)
LSb
dsPIC30F2011/2012/3012/3013
SDO1
SCK1
SDI1
Serial Clock
13.5
When the device enters Idle mode, all clock sources
remain functional. The SPISIDL bit (SPI1STAT<13>)
selects if the SPI module will stop or continue on idle. If
SPISIDL = 0, the module will continue to operate when
the CPU enters Idle mode. If SPISIDL = 1, the module
will stop when the CPU enters Idle mode.
SDO1
SCK1
SDI1
SPI Operation During CPU Idle
Mode
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SPI1BUF)
(SPI1SR)
SPI Slave
LSb
DS70139F-page 93