ATMEGA168-20PU Atmel, ATMEGA168-20PU Datasheet
ATMEGA168-20PU
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ATMEGA168-20PU Summary of contents
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... Temperature Range: ° ° – - • Speed Grade: – ATmega48V/88V/168V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega48/88/168 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V ® 8-Bit Microcontroller 8-bit Microcontroller with 8K Bytes In-System Programmable Flash ATmega48/V ATmega88/V ATmega168/V Preliminary Rev. 2545E–AVR–02/05 ...
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Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240µA 32 kHz, 1.8V: 15µA (including Oscillator) – Power-down Mode: 0.1µA at 1.8V 1. Pin Configurations Figure 1-1. Pinout ATmega48/88/168 TQFP Top View (PCINT19/OC2B/INT1) PD3 1 (PCINT20/XCK/T0) PD4 2 GND ...
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Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2. Overview The ATmega48/88/168 ...
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... C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu- lators, and Evaluation kits. 2.2 Comparison Between ATmega48, ATmega88, and ATmega168 The ATmega48, ATmega88 and ATmega168 differ only in memory sizes, boot loader support, and interrupt vector sizes. for the three devices. Table 2-1. ...
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In ATmega48, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. 2.3 Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB7..0) XTAL1/XTAL2/TOSC1/TOSC2 Port B ...
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The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in 78. 2.3 the supply ...
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AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 4.5 General Purpose Register File The Register File is optimized for the ...
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The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 4-4 vard architecture and the fast-access Register ...
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... The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see and ATmega168” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...
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Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); ...
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... Since all AVR instructions are bits wide, the Flash is orga- nized as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Loader Section and Application Program Section in ATmega88 and ATmega168. ATmega48 does not have separate Boot Loader and Application Program sections, and the SPM instruction can be executed from the entire Flash. See SELFPRGEN description in section ” ...
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... Figure 5-1. Figure 5-2. ATmega48/88/168 16 Program Memory Map, ATmega48 Program Memory Application Flash Section Program Memory Map, ATmega88 and ATmega168 Program Memory Application Flash Section Boot Flash Section 0x0000 0x7FF 0x0000 0x0FFF/0x1FFF 2545E–AVR–02/05 ...
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SRAM Data Memory Figure 5-3 The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space ...
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Figure 5-4. 5.3 EEPROM Data Memory The ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM ...
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... Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See Support – Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 264 details about Boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out ...
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When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is ...
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Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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I/O Memory The I/O space definition of the ATmega48/88/168 is shown in All ATmega48/88/168 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...
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System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
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Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time ...
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Table 6-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V delay will not monitor the actual voltage and it will be ...
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Figure 6-2. The Low Power Oscillator can operate in three different modes, each optimized for a specific fre- quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in on page Table 6-3. Frequency Range Notes: The ...
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Table 6-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 6.4 Full Swing Crystal Oscillator Pins XTAL1 and XTAL2 are input and output, respectively inverting amplifier ...
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Figure 6-3. Table 6-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, BOD enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast ...
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Low Frequency Crystal Oscillator The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Fre- quency Crystal Oscillator. The crystal should be connected as shown in Oscillator is selected, start-up times are determined ...
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When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-9 on page Table 6-9. Power Conditions BOD enabled Fast rising power Slowly rising power Note: 6.6.1 Oscillator Calibration Register – OSCCAL Bit ...
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Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock by ...
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Table 6-13. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in ...
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CPU's clock frequency. Hence not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch ...
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Table 6-14. CLKPS3 ATmega48/88/168 36 Clock Prescaler Select CLKPS2 CLKPS1 ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 7.1 Idle Mode When the SM2..0 bits are written to 000, ...
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If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt ...
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Power Reduction Register - PRR Bit Read/Write Initial Value • Bit 7 - PRTWI: Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the ...
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Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...
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Refer to the section which pins are enabled. If the input buffer is enabled and the input signal is left floating or have ...
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... During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the ATmega168, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48 and ATmega88, the instruction placed at the Reset Vector must be an RJMP – ...
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Figure 8-1. BODLEVEL [2..0] RSTDISBL Table 8-1. Symbol V POT V RST t RST Notes: 8.0.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be ...
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Figure 8-2. TIME-OUT INTERNAL Figure 8-3. TIME-OUT INTERNAL 8.0.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate ...
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Brown-out Detection ATmega48/88/168 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The ...
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Figure 8-5. 8.0.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page ...
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Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 0 – PORF: Power-on ...
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Watchdog Timer ATmega48/88/168 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms ...
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In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...
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Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...
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Watchdog Timer Control Register - WDTCSR Bit Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for interrupt. ...
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Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown ...
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... Each Interrupt Vector occupies two instruction words in ATmega168, and one instruction word in ATmega48 and ATmega88. • ATmega48 does not have a separate Boot Loader Section. In ATmega88 and ATmega168, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR ...
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Table 9-1. Reset and Interrupt Vectors in ATmega48 (Continued) Vector No. Program Address 24 0x017 25 0x018 26 0x019 The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega48 is: Address Labels Code 0x000 ...
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... When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see ”Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 264. 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section ...
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Table 9-3. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88 is: Address Labels Code 0x000 0x001 0x002 0x003 0x004 0x005 0x006 0x007 0X008 0x009 0x00A 0x00B 0x00C 0x00D 0x00E 0x00F ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and ...
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... Interrupt Vectors in ATmega168 Table 9-4. Reset and Interrupt Vectors in ATmega168 Program (2) VectorNo. Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 5 0x0008 6 0x000A 7 0x000C 8 0x000E 9 0x0010 10 0x0012 11 0x0014 12 0x0016 13 0x0018 14 0x001A 15 0x001C 16 0x001E 17 0x0020 18 0x0022 19 0x0024 20 0x0026 21 0x0028 ...
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... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in ATmega168 IVSEL Reset Address 0 ...
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... When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega168 is: Address Labels Code .org 0x0002 0x0002 0x0004 ... ...
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... Moving Interrupts Between Application and Boot Space, ATmega88 and ATmega168 The MCU Control Register controls the placement of the Interrupt Vector table. 9.3.2 MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory ...
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is ...
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I/O-Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 10-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
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Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out ; Insert nop for synchronization nop ; Read port pins in ... C Code Example unsigned char i; ... ...
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Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable ...
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Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...
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MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
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Oscillator amplifier. In this mode, a crystal Oscillator is con- nected to this pin, and the pin cannot be used as an I/O pin. PCINT7: Pin Change Interrupt source 7. The PB7 pin can ...
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When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTB2 bit. ...
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Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATmega48/88/168 74 Overriding Signals for Alternate Functions in PB7..PB4 PB7/XTAL2/ PB6/XTAL1/ ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 10-6. Port Pin The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL ...
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Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than the input signal, and the pin is driven by an open drain driver with slew- rate limitation. ...
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Table 10-7 shown in Table 10-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Table 10-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 2545E–AVR–02/05 and Table 10-8 relate the alternate ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 10-9. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, ...
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T1/OC0B/PCINT21 – Port D, Bit 5 T1, Timer/Counter1 counter source. OC0B, Output Compare Match output: The PD5 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PD5 pin has to be configured as an ...
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Table 10-10. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 10-11. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI ...
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Register Description for I/O Ports 10.4.1 The Port B Data Register – PORTB Bit Read/Write Initial Value 10.4.2 The Port B Data Direction Register – DDRB Bit Read/Write Initial Value 10.4.3 The Port B Input Pins Address – PINB ...
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The Port D Input Pins Address – PIND Bit Read/Write Initial Value ATmega48/88/168 PIND7 PIND6 PIND5 PIND4 N/A N/A N/A N PIND3 PIND2 PIND1 PIND0 R ...
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External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT23..0 pins are configured as ...
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External Interrupt Control Register A – EICRA The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/Write Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, ...
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External Interrupt Mask Register – EIMSK Bit Read/Write Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 1 – INT1: External Interrupt Request ...
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Pin Change Interrupt Control Register - PCICR Bit Read/Write Initial Value • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 2 - PCIE2: Pin Change ...
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Bit 0 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), ...
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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • ...
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Definitions Many register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com- pare Unit, in this case ...
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Figure 12-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 12-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) strobe bits in ...
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PWM refer to A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be ...
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Figure 12-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 12-6. Fast PWM Mode, ...
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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 12.6.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...
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OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (see visible on the port pin if the data direction for the port pin is ...
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Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 12-10 mode and PWM mode, where OCR0A is TOP. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk I/O TCNTn ...
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Timer/Counter Register Description 12.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
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Table 12-4 rect PWM mode. Table 12-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...
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Table 12-7 rect PWM mode. Table 12-7. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM01:0: ...
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Timer/Counter Control Register B – TCCR0B Bit Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...
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Table 12-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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Timer/Counter Interrupt Mask Register – TIMSK0 Bit Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare ...
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Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one ...
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Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Figure 13-1. 16-bit Timer/Counter Block Diagram Note: 13.1.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
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Section “13.6” on page (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICP1) ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example unsigned int TIM16_ReadTCNT1( void ) ...
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Assembly Code Example TIM16_WriteTCNT1: C Code Example void TIM16_WriteTCNT1( unsigned int Note: The assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to TCNT1. 13.2.1 Reusing the Temporary High ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 Figure 13-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 13.5 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
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TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written ...
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I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 13.6 Output Compare Units The 16-bit comparator continuously compares ...
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PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer ...
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Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x ...
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PWM refer to page 129. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. ...
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Figure 13-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define ...
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit ...
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When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next ...
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OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...
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TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...
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OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively ...
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Figure 13-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f (clk TCNTn OCRnx OCFnx Figure 13-12 frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced ...
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Figure 13-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 2545E–AVR–02/05 clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) ...
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Timer/Counter Register Description 13.10.1 Timer/Counter1 Control Register A – TCCR1A Bit Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 ...
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Table 13-3 correct or the phase and frequency correct, PWM mode. Table 13-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of ...
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Table 13-4. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 13.10.4 Timer/Counter1 – TCNT1H and TCNT1L ...
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Input Capture Register 1 – ICR1H and ICR1L Bit Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for ...
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Timer/Counter1 Interrupt Flag Register – TIFR1 Bit Read/Write Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATmega48/88/168, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input ...
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Timer/Counter0 and Timer/Counter1 Prescalers ”8-bit Timer/Counter0 with PWM” on page 88 106 share the same prescaler module, but the Timer/Counters can have different prescaler set- tings. The description below applies to both Timer/Counter1 and Timer/Counter0. 14.0.1 Internal Clock Source ...
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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...
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General Timer/Counter Control Register – GTCCR Bit Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the ...
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Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width ...
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Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...
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Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...
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Figure 15-3. Output Compare Unit, Block Diagram The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...
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The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com- pare (FOC2x) strobe bit in ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1 tells the Waveform Generator that no action on the OC2x Register ...
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Figure 15-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for ...
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OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 15.6.4 Phase Correct PWM Mode ...
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COM2x1:0 to three. TOP is defined as 0xFF when WGM2 and OCR2A when MGM2 (See value will only be visible on the port pin if the data direction for ...
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Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 15-10 Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 15-11 Figure 15-11. Timer/Counter Timing Diagram, Clear ...
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Timer/Counter Register Description 15.8.1 Timer/Counter Control Register A – TCCR2A Bit Read/Write Initial Value • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of ...
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Table 15-4 rect PWM mode. Table 15-4. COM2A1 Note: • Bits 5:4 – COM2B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits ...
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Table 15-7 rect PWM mode. Table 15-7. COM2B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATmega48/88/168 and will always read as zero. • Bits 1:0 – WGM21:0: ...
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Timer/Counter Control Register B – TCCR2B Bit Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future ...
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Table 15-9. CS22 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...
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Timer/Counter2 Interrupt Mask Register – TIMSK2 Bit Read/Write Initial Value • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set ...
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Asynchronous operation of the Timer/Counter 15.9.1 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be ...
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Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, ...
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Bit 3 – OCR2AUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hard- ware. A ...
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Timer/Counter Prescaler Figure 15-12. Prescaler for Timer/Counter2 TOSC1 PSRASY The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 ...
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Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega48/88/168 and peripheral devices or between several AVR devices. The ATmega48/88/168 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer ...
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Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line ...
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Table 16-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction ...
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Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ; Enable SPI, Master, set clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for transmission complete ...
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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 2545E–AVR–02/05 (1) ; ...
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SS Pin Functionality 16.1.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted ...
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SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and ...
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Table 16-5. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 16-3. SPI Transfer Format with CPHA = 0 Figure 16-4. SPI Transfer Format with CPHA = 1 2545E–AVR–02/05 CPOL Functionality Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup ...
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USART0 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master ...
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Figure 17-1. USART Block Diagram Note: 17.2 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave ...
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Figure 17-2. Clock Generation Logic, Block Diagram DDR_XCKn Signal description: txclk rxclk xcki operation. xcko fosc 17.2.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. ...
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Table 17-1 ing the UBRRn value for each mode of operation using an internally generated clock source. Table 17-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f ...
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External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. ...
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A frame starts with the start bit followed by the least significant data bit. Then the next data bits total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted ...
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USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...
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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: C Code Example #define FOSC 1843200 // Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) ...
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Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by ...
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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8 bit in UCS- RnB before the low byte of the character is written to UDRn. The ...
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Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) ...
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The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be ...
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Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer error, return -1 andi r18,(1<<FEn)|(1<<DORn)|(1<<UPEn) breq USART_ReceiveNoError ldi ldi ...
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Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data ...
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until ...
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Figure 17-5. Start Bit Sampling When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the ...
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Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop ...
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Table 17-2. # (Data+Parity Bit) Table 17-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...
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When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit ...
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USART Register Description 17.9.1 USART I/O Data Register n– UDRn Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...
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UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when ...
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Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, ...
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Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
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Table 17-8. UCPOLn 0 1 17.9.5 USART Baud Rate Registers – UBRRnL and UBRRnH Bit Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be ...
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Table 17-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc U2Xn = 0 U2Xn = 1 Baud Rate UBRR UBRR (bps) n Error n 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 ...
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Table 17-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc U2Xn = 0 U2Xn = 1 Baud Rate UBRR UBRR (bps) n Error n 2400 95 0.0% 191 4800 47 0.0% 95 9600 ...
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Table 17-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc U2Xn = 0 U2Xn = 1 Baud Rate UBRR UBRR (bps) n Error n 2400 207 0.2% 416 4800 103 0.2% 207 9600 ...
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Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc U2Xn = 0 U2Xn = 1 Baud Rate UBRR UBRR (bps) n Error n 2400 416 -0.1% 832 4800 207 0.2% 416 9600 ...
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USART in SPI Mode The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the follow- ing features: • Full Duplex, Three-wire ...
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Table 18-1. Operating Mode Synchronous Master mode Note: BAUD f OSC UBRRn 18.3 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn ...
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Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB ...
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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example USART_Init: C Code Example void USART_Init( unsigned int baud ) { } ...
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After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ- ing to the UDRn I/O location. This is the case for both sending and receiving data since the transmitter controls the transfer clock. ...