PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet
PIC18F6410-I/PT
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... PIC18F6310/6410/8310/8410 64/80-Pin Flash Microcontrollers 2010 Microchip Technology Inc. with nanoWatt XLP Technology Data Sheet DS39635C ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Four 8-Bit/16-Bit Timer/Counter modules • Capture/Compare/PWM (CCP) modules Program Memory (On-Board/External) Device Flash # Single-Word (bytes) Instructions PIC18F6310 8K/0 4096/0 PIC18F6410 16K/0 8192/0 PIC18F8310 8K/2M 4096/1M PIC18F8410 16K/2M 8192/1M 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Peripheral Highlights (Continued): • Master Synchronous Serial Port (MSSP) module ...
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... RG0/CCP3 3 RG1/TX2/CK2 4 RG2/RX2/DT2 5 RG3 6 RG5/MCLR RG4 RF7/SS 11 RF6/AN11 12 RF5/AN10/CV REF 13 RF4/AN9 14 RF3/AN8 15 RF2/AN7/C1OUT 16 RE7 is the alternate pin for CCP2 multiplexing Note 1: DS39635C-page PIC18F6310 PIC18F6410 RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI/RA7 RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA 35 RC3/SCK/SCL 34 RC2/CCP1 2010 Microchip Technology Inc. ...
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... RG2/RX2/DT2 7 RG3 8 RG5/MCLR RG4 RF7/SS 13 RF6/AN11 14 RF5/AN10/CV REF 15 RF4/AN9 16 RF3/AN8 17 RF2/AN7/C1OUT 18 RH7 19 RH6 RE7 is the alternate pin for CCP2 multiplexing Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F8310 PIC18F8410 RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 57 RB2/INT2 56 (1) RB3/INT3/CCP2 55 RB4/KBI0 54 RB5/KBI1 53 RB6/KBI2/PGC OSC2/CLKO/RA6 50 OSC1/CLKI/RA7 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 397 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 397 Index .................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 409 Customer Change Notification Service .............................................................................................................................................. 409 Customer Support .............................................................................................................................................................................. 409 Reader Response .............................................................................................................................................................................. 410 PIC18F6310/6410/8310/8410 Product Identification System ............................................................................................................ 411 DS39635C-page 6 2010 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 7 ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 8 2010 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F6310 • PIC18LF6310 • PIC18F6410 • PIC18LF6410 • PIC18F8310 • PIC18LF8310 • PIC18F8410 • PIC18LF8410 This family offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price. In addition to ...
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... DS39635C-page 10 1.3 Details on Individual Family Members Devices in the PIC18F6310/6410/8310/8410 family are available in 64-pin (PIC18F6310/8310) and 80-pin (PIC18F6410/8410) packages. Block diagrams for the two groups are shown in Figure 1-1 respectively. The devices are differentiated from each other in three ways: 1. Flash Program Memory: 8 Kbytes in PIC18FX310 devices, 16 Kbytes in PIC18FX410 devices ...
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... Input Channels 12 Input Channels 12 Input Channels 12 Input Channels Resets (and Delays) RESET Instruction, Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set 83 with Extended Packages 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 PIC18F6310 PIC18F6410 DC – 40 MHz DC – 40 MHz 8K 16K 4096 8192 768 768 No No ...
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... RC1/T1OSI/CCP2 (1) RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 PORTD RD7/PSP7:RD0/PSP0 PORTE 8 RE0/RD RE1/WR RE2/CS RE3 RE4 RE5 RE6 (1) RE7/CCP2 PORTF RF0/AN5 RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/CV REF RF6/AN11 RF7/SS PORTG RG0/CCP3 RG1/TX2/CK2 RG2/RX2/DT2 RG3 RG4 (2) RG5 /MCLR/V PP 2010 Microchip Technology Inc. ...
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... RG5 is only available when MCLR functionality is disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. 3: Refer to Section 3.0 “Oscillator Configurations” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Latch 8 8 Data Memory ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Default assignment for CCP2 when Configuration bit, CCP2MX, is set. Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Default assignment for CCP2 when Configuration bit, CCP2MX, is set. Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... Parallel Slave Port data. I/O ST Digital I/O. I/O TTL Parallel Slave Port data. I/O ST Digital I/O. I/O TTL Parallel Slave Port data. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Default assignment for CCP2 when Configuration bit, CCP2MX, is set. Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTE is a bidirectional I/O port. I/O ST Digital I/O ...
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... Analog Input 10. O Analog Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog Input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels I = Input P = Power Default assignment for CCP2 when Configuration bit, CCP2MX, is set. Note 1: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... External Memory Address/Data 6. I/O TTL Parallel Slave Port data. I/O ST Digital I/O. I/O TTL External Memory Address/Data 7. I/O TTL Parallel Slave Port data. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... Analog Input 10. O Analog Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog Input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Note 1: Microcontroller mode). Default assignment for CCP2 in all operating modes (CCP2MX is set). 2: Alternate assignment for CCP2 when CCP2MX is cleared (Microcontroller mode only). 3: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. P — Ground reference for analog modules. P — Positive supply for analog modules. CMOS = CMOS compatible input or output Analog = Analog input O = Output with I Description 2 C™ or SMB levels 2010 Microchip Technology Inc. ...
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... REF REF reference for analog modules is implemented The AV and AV pins must always be Note connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure 2-1. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 FIGURE 2- MCLR ( Pin” ...
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... V DD Not all devices incorporate software BOR Note: control. See device-specific information. may result in a spontaneous DD does not approach the set point. DD and circuit as the microcontroller for Section 5.0 “Reset” 2010 Microchip Technology Inc. ...
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... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V and V specifications are met 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2.4 ICSP Pins device The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It ...
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... Bottom Layer Copper Pour (tied to ground) OSCO GND Devices” OSCI DEVICE PINS SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Primary Oscillator Crystal DEVICE PINS OSC1 ` OSC2 GND ` T1OSO T1OS Oscillator: C2 Top Layer Copper Pour (tied to ground) C2 Oscillator Crystal C1 2010 Microchip Technology Inc. ...
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... Figure 3-1 the pin connections. The oscillator design requires the use of a parallel resonant crystal. Use of a series resonant crystal may give a Note: frequency out of the crystal manufacturer’s specifications. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 FIGURE 3-1: (1) C1 (1) C2 Note 1: See C1 and C2 ...
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... Mode) OSC2 Open shows the pin connections for the EC EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC Figure 3-4 shows the pin connections EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX RA6 I/O (OSC2) 2010 Microchip Technology Inc. ...
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... Recommended values: 3 k R 100 k EXT C > EXT 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who want to use a lower frequency oscillator circuit clock the device up to its highest rated frequency from a crystal oscillator ...
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... Three compensation techniques are dis- cussed in Section 3.6.5.1 “Compensating with the AUSART”, Section 3.6.5.2 “Compensating with the Timers”” and Timers”, but other techniques may be used. the Section 3.7.1 Register”. Section 3.6.5.3 “Compensating with 2010 Microchip Technology Inc. ...
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... Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Note 1: Section 3.6.4 “PLL in INTOSC Modes” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register ...
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... FOSC<3:0> 010 125 kHz 001 31 kHz 1 000 0 OSCTUNE<7> 2010 Microchip Technology Inc. and 3-8. See Section 24.0 Peripherals CPU IDLEN Clock Control OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Start-up ...
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... The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabi- lized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON< ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see 2: Default output frequency of INTOSC on Reset. 3: DS39635C-page 42 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) Section 3.6.3 “OSCTUNE R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown Register”. 2010 Microchip Technology Inc. ...
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... See Table 5-2 in Note 1: Section 5.0 “Reset” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 3.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 44 2010 Microchip Technology Inc. ...
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... IDLEN reflects its value when the SLEEP instruction is executed. Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 4.1.1 CLOCK SOURCES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. 2010 Microchip Technology Inc. Section 3.7.1 “Oscillator Figure 4-1), the primary ...
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... OST OSC PLL 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator Figure 4-2) ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled 2010 Microchip Technology Inc. Figure 4-4). When the clock ...
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... TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 INTOSC Multiplexer OSC1 T PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS<1:0> bits Changed Note 1024 OST OSC PLL 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 n-1 n Clock Transition OST (1) PLL ( n-1 n Clock Transition ...
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... IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS<1:0> bits (1) PLL OSTS bit Set CSD 27-12), while it becomes ready 2010 Microchip Technology Inc. ...
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... Peripheral Clock Program Counter Wake Event 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, T required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions ...
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... INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. after an interval of T IOBST 27-12). Clocks to the peripherals 2010 Microchip Technology Inc. ...
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... SLEEP or CLRWDT instruction, losing a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 4.5.3 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready ...
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... Section 4.4 “Idle Modes”). is the PLL Lock-out Timer (Parameter F12 (Parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status Bit (OSCCON) OSTS (2) — IOFS (4) OSTS (4) rc (2) — (5) IOFS (5) OSTS (4) rc (2) — IOFS (4) OSTS (4) rc (2) — (5) IOFS 2010 Microchip Technology Inc. ...
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... PWRT 65.5 ms INTRC 11-Bit Ripple Counter See Table 5-2 for time-out situations. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39635C-page 56 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 POR BOR bit Bit is unknown 2010 Microchip Technology Inc. ...
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... If these conditions are not met, the device must be held in Reset until the operating conditions are met. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a POR occurs; ...
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... BOR is disabled; must be enabled by reprogramming the Configuration bits. BOR is enabled in software; operation controlled by SBOREN. BOR is enabled in hardware and active during the Run and Idle modes; disabled during Sleep mode. BOR is enabled in hardware; must be disabled by reprogramming the Configuration bits. and operates as previously 2010 Microchip Technology Inc. ...
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... INTIO1, INTIO2 (65.5 ms) is the nominal Power-up Timer (PWRT) delay. Note the nominal time required for the PLL to lock. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 5.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly different from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39635C-page PWRT T OST T PWRT T OST T PWRT T OST 2010 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. T PLL 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 , V RISE > PWRT T OST T PWRT ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. Table 5-3. RCON Register SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( STKPTR Register POR BOR STKFUL STKUNF 2010 Microchip Technology Inc. ...
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... Reset value for specific condition. 4: Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read ‘0’. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, WDT Reset ...
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... Reset value for specific condition. 4: Bits, 6 and 7 of PORTA, LATA and TRISA, are enabled depending on the oscillator mode selected. When 5: not enabled as PORTA pins, they are disabled and read ‘0’. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 MCLR Resets Power-on Reset, WDT Reset ...
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... NOP instruction). The PIC18F6310 and PIC18F8310 each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The PIC18F6410 and PIC18F8410 each have 16 Kbytes of Flash memory and can store up to Section 7.0 8,192 single-word instructions. ...
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... Flash memory. Attempts to read above the physical limit of the on-chip Flash (3FFFh) causes a read of all ‘0’s (a NOP instruction). The Microcontroller mode is also the only operating mode available to PIC18F6310 and PIC18F6410 devices. REGISTER 6-1: CONFIG3L: CONFIGURATION BYTE REGISTER LOW R/P-1 R/P-1 ...
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... Table Read Mode From Microcontroller Yes Extended Yes Microcontroller Microprocessor No Access No Access Microprocessor Yes w/Boot Block 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Extended Microcontroller Mode 000000h (Top of Memory) (Top of Memory 1FFFFFh Microprocessor with Boot Block Mode 000000h 0007FFh 000800h (No (Top of Memory 1FFFFFh ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack<20:0> 11111 11110 11101 00011 001A34h Top-of-Stack 00010 000D58h 00001 00000 to by the STKPTR register can return these values to Stack Pointer STKPTR<4:0> 00010 2010 Microchip Technology Inc. ...
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... SP<4:0>: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software POR. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Table Latch (TABLAT) register contains the data that is read from the program memory. Data is transferred from program memory one byte at a time. Table read operation is discussed Section 7.1 “Table Reads and Table 2010 Microchip Technology Inc. further in Writes”. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 6.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG3 ; continue code Figure 6-5 shows how the Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h shows how this works. Section 6.5 “Data Memory and the for Instruction Set” 2010 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank” detailed description of the Access RAM. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 6.3.1 BANK SELECT REGISTER Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh 2010 Microchip Technology Inc. ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Data Memory 000h 7 ...
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... LATB F6Ah — (2) LATA F69h — (3) (2) PORTJ F68h — (3) (2) PORTH F67h — (2) PORTG F66h — (2) PORTF F65h — (2) PORTE F64h — PORTD F63h — (2) (2) PORTC F62h — (2) PORTB F61h — (2) PORTA F60h — 2010 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. 5: When disabled, these bits read as ‘0’. STKFUL and STKUNF bits are cleared by user software POR. 6: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 4 Bit 3 Bit 2 Bit 1 Top-of-Stack Upper Byte (TOS< ...
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... CCP2M0 65, 167 --00 0000 65, 168 xxxx xxxx 65, 168 0000 0000 CCP3M0 65, 167 --00 0000 CVR0 65, 271 0000 0000 CM0 65, 265 0000 0111 65, 163 0000 0000 65, 165 0000 0000 TMR3ON 65, 163 0000 0000 — 65, 149 0000 ---- Section 3.6.4 “PLL in 2010 Microchip Technology Inc. ...
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... RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. 5: When disabled, these bits read as ‘0’. STKFUL and STKUNF bits are cleared by user software POR. 6: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 4 Bit 3 Bit 2 ...
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... ADDEN FERR OERR Value on Details Bit 0 POR, BOR on page: 66, 221 0000 0000 ABDEN 66, 220 0100 0-00 66, 234 0000 0000 66, 248 0000 0000 66, 246 xxxx xxxx TX9D 66, 242 0000 -010 RX9D 66, 243 0000 000x Section 3.6.4 “PLL in 2010 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the sec- 2: ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 intended example, CLRF STATUS, will set the Z bit and leave the remaining Status bits unchanged 6-3, contains (‘ ...
Page 84
... INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE 2010 Microchip Technology Inc. Bank”) as the data Register”) are used with other Stack Pointer ; Clear INDF ; register then ; inc pointer ; All done with ; Bank1? ; NO, clear next ...
Page 85
... PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair ...
Page 86
... Figure 6-9. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in “Extended Instruction Syntax”. 2010 Microchip Technology Inc. Section 25.2.1 ...
Page 87
... The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 000h 060h Bank 0 100h Bank 1 through ...
Page 88
... PIC18 instruction set. These instructions are executed as described in Section 25.2 “Extended Instruction Bank 0 Bank 0 Bank 1 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Set”. 00h Bank 1 “Window” 5Fh Bank 0 7Fh 80h SFRs FFh Access Bank 2010 Microchip Technology Inc. ...
Page 89
... Note 1: The Table Pointer register points to a byte in the program memory space. 2: Data is actually written to the memory location by the memory write algorithm. See “Writing to Program Memory Space (PIC18F8310/8410 only)” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide ...
Page 90
... TABLAT. A typical method for reading data from program memory is shown in Example TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer Figure 7-2 7-1. 2010 Microchip Technology Inc. ...
Page 91
... TBLRD*+ MOVF TABLAT, W MOVWF WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Program Memory Space (Odd Byte Address) TBLPTR = xxxxx1 TBLRD ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ; read into TABLAT and increment ...
Page 92
... Microchip document “Programming Specifications for PIC18FX410/X490 Flash MCUs” (DS39624). 7.7 Flash Program Operation During Code Protection See Section 24.5 “Program Verification and Code Protection” for details on code protection of Flash program memory. 2010 Microchip Technology Inc. operations for ...
Page 93
... TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) TABLAT Program Memory Table Latch Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 4 Bit 3 Bit 2 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ...
Page 94
... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 94 2010 Microchip Technology Inc. ...
Page 95
... The external memory interface is not Note: implemented on PIC18F6310 PIC18F6410 (64-pin) devices. The external memory interface allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE and PORTH) are ...
Page 96
... EBDIS = 1, the pins will switch to external bus. If the EBDIS bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. At that time, the pins will change from external bus to I/O ports. 2010 Microchip Technology Inc. ...
Page 97
... OE WRH WRL Note 1: This signal only applies to table writes. See 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 For all 16-bit modes, the Address Latch Enable (ALE) pin indicates that the address bits, A<15:0>, are avail- able on the external memory interface bus. Following the ...
Page 98
... A<20:1> 373 A<x:0> D<15:0> D<15:0> CE 373 Address Bus Data Bus Control Lines Section 7.1 “Table Reads and Table 2010 Microchip Technology Inc odd address JEDEC Word EPROM Memory ( Writes”. ...
Page 99
... This signal only applies to table writes. See Note 1: Demultiplexing is only required when multiple memory devices are accessed. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 100
... TBLRD Cycle 0Ch CF33h Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 9256h ‘1’ ‘1’ ‘0’ Wait 9256h Opcode Fetch ADDLW 55h from 000104h MOVLW 2010 Microchip Technology Inc. ...
Page 101
... CE ALE OE Memory Opcode Fetch Cycle SLEEP from 007554h Instruction Execution INST(PC – 2) Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 00h 3AABh 0E55h Opcode Fetch Sleep Mode, MOVLW 55h from 007556h ...
Page 102
... AD<15:0> bus. The appropriate level of the BA0 control line is strobed on the LSb of the TBLPTR. D<7:0> A<19:0> 373 D<15:8> Address Bus Data Bus Control Lines Section 7.1 “Table Reads and Table 2010 Microchip Technology Inc. A<x:1> A0 D<7:0> ...
Page 103
... FIGURE 8-9: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE A<19:16> AD<15:8> AD<7:0> CE ALE OE Opcode Fetch Memory Cycle TBLRD * from 000100h Instruction INST(PC – 2) Execution 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 0Eh 55h 33h Table Read of 92h from 199E67h TBLRD Cycle 2 ...
Page 104
... SLEEP from 007554h Instruction INST(PC – 2) Execution Bus becomes inactive regardless of power-managed mode entered when SLEEP is executed. Note 1: DS39635C-page 104 00h 3Ah 0Eh ABh 55h Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP (1) Bus Inactive 2010 Microchip Technology Inc. ...
Page 105
... CONFIG3H MCLRE — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the external memory interface. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 If operations in a lower power Run mode are antici- pated, users should provide in their applications for adjusting memory access times at the lower clock speeds ...
Page 106
... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 106 2010 Microchip Technology Inc. ...
Page 107
... Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply Without Hardware Multiply Unsigned Hardware Multiply Without Hardware Multiply Signed Hardware Multiply 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 EXAMPLE 9-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 9-2: MOVF ARG1, W MULWF ARG2 ...
Page 108
... MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; 2010 Microchip Technology Inc. ...
Page 109
... Individual interrupts can be disabled through their corresponding enable bits. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are devices ...
Page 110
... IPEN GIEL/PEIE IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP 2010 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEH/GIE GIEL/PEIE ...
Page 111
... None of the RB<7:4> pins have changed state A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and Note 1: allow the bit to be cleared. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Interrupt flag bits are set when an interrupt Note: ...
Page 112
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39635C-page 112 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 113
... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding Note: enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 ...
Page 114
... R-0 R/W-0 R/W-0 TX1IF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Enable bit, GIE should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 115
... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R/W-0 R/W-0 — BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 116
... A TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. DS39635C-page 116 R-0 U-0 U-0 TX21F — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 — CCP3IF bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 117
... TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 TX1IE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 118
... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39635C-page 118 U-0 R/W-0 R/W-0 — BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown ...
Page 119
... TX2IE: AUSART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3-1 Unimplemented: Read as ‘0’ bit 0 CCP3IE: CCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R-0 U-0 U-0 TX2IE — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 120
... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39635C-page 120 R/W-1 R/W-1 R/W-1 TX1IP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 121
... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 U-0 R/W-1 R/W-1 — BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 122
... Unimplemented: Read as ‘0’ bit 0 CCP3IP: CCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39635C-page 122 R-1 U-0 U-0 TX21P — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — CCP3IP bit Bit is unknown 2010 Microchip Technology Inc. ...
Page 123
... PD: Power-Down Detection Flag bit For details of bit operation, see bit 1 POR: Power-on Reset Status bit For details of bit operation, see bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
Page 124
... Example 10-1 STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Section 12.0 Section 6.3 saves and restores the WREG, 2010 Microchip Technology Inc. ...
Page 125
... Port I/O pins have diode protection to V Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 11.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 126
... PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. I ANA Main oscillator input connection. I ANA Main clock input connection. O DIG LATA<7> data output. Disabled in External Oscillator modes. I TTL PORTA<7> data input. Disabled in External Oscillator modes. Description /4) in all oscillator modes except OSC 2010 Microchip Technology Inc. ...
Page 127
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. RA<7:6> and their associated latch and data direction bits are enabled as I/O pins based on oscillator Note 1: configuration; otherwise, they are read as ‘0’. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 ...
Page 128
... Microcontroller mode. If the device is in Microcontroller mode, the alternate assignment for CCP2 is RE7. As with other CCP2 con- figurations, the user must ensure that the TRISB<3> bit is set appropriately for the intended operation. 2010 Microchip Technology Inc. device from delay. CY ...
Page 129
... Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared (Microprocessor, Extended Note 1: Microcontroller and Microcontroller with Boot Block modes, 80-pin devices only); default assignment is RC1. All other pin functions are disabled when ICSP or ICD operations are enabled. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type ...
Page 130
... Legend: Shaded cells are not used by PORTB. DS39635C-page 130 Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF INT3IE INT2IE INT1IE INT3IF Reset Bit 1 Bit 0 Values on Page RB1 RB0 INT0IF RBIF 63 INT3IP RBIP 63 INT2IF INT1IF 63 2010 Microchip Technology Inc. ...
Page 131
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 On a Power-on Reset, these pins are Note: configured as digital inputs ...
Page 132
... LATC<7> data output PORTC<7> data input Asynchronous serial receive data input (EUSART module) O DIG Synchronous serial data output (EUSART module); takes priority over port data Synchronous serial data input (EUSART module). User must configure as an input. Description 2010 Microchip Technology Inc. ...
Page 133
... TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC Output Latch Register TRISC PORTC Data Direction Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset Bit 1 Bit 0 Values ...
Page 134
... EXAMPLE 11-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2010 Microchip Technology Inc. ...
Page 135
... Don’t care (TRIS bit does not affect port direction or is overridden for this option). External memory interface I/O takes priority over all other digital and PSP I/O. Note 1: Implemented on 80-pin devices only. 2: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type ...
Page 136
... External memory interface, Data Bit 7 input O DIG PSP read data output (LATD<7>); takes priority over port data. I TTL PSP write data input. Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 Description (1) . (1) . Reset Bit 1 Bit 0 Values on Page RD1 RD0 2010 Microchip Technology Inc. ...
Page 137
... When the interface is enabled (80-pin devices only), PORTE is the high-order byte of the multiplexed address/data bus (AD<15:8>). The TRISE bits are also overridden. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 When the Parallel Slave Port is active on PORTD, three of the PORTE pins (RE0/AD8/RD, RE1/AD9/WR and RE2/AD10/CS) are configured as digital control inputs for the port ...
Page 138
... CCP2 compare output and CCP2 PWM output; takes priority over port data CCP2 capture input. O DIG External memory interface, Address/Data Bit 15 output. I TTL External memory interface, Data Bit 15 input. Description (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) 2010 Microchip Technology Inc. ...
Page 139
... TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 PORTE RE7 RE6 LATE LATE Output Latch Register TRISE PORTE Data Direction Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 Reset Bit 1 Bit 0 Values ...
Page 140
... MOVLW 0x07 ; MOVWF CMCON ; Turn off comparators MOVLW 0x0F ; MOVWF ADCON1 ; Set PORTF as digital I/O MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISF ; Set RF3:RF0 as inputs ; RF5:RF4 as outputs ; RF7:RF6 as inputs 2010 Microchip Technology Inc. ...
Page 141
... ADCON1 — — CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATF<0> data output; not affected by analog input PORTF<0> data input; disabled when analog input is enabled. ...
Page 142
... CLRF PORTG ; Initialize PORTG by ; clearing output ; data latches CLRF LATG ; Alternate method ; to clear output ; data latches MOVLW 0x04 ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as inputs ) is an input PP INITIALIZING PORTG 2010 Microchip Technology Inc. ...
Page 143
... LATG — — TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. RG5 is available as an input only when MCLR is disabled. Note 1: 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATG<0> data output PORTG< ...
Page 144
... EXAMPLE 11-8: INITIALIZING PORTH CLRF PORTH ; Initialize PORTH by ; clearing output ; data latches CLRF LATH ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISH ; Set RH3:RH0 as inputs ; RH5:RH4 as outputs ; RH7:RH6 as inputs 2010 Microchip Technology Inc. ...
Page 145
... Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 TRISH PORTH Data Direction Register PORTH RH7 RH6 LATH PORTH Output Latch Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATH<0> data output PORTH<0> data input. O DIG External memory interface, Address Line 16 ...
Page 146
... EXAMPLE 11-9: CLRF PORTJ CLRF LATJ MOVLW 0xCF MOVWF TRISJ INITIALIZING PORTJ ; Initialize PORTG by ; clearing output ; data latches ; Alternate method ; to clear output ; data latches ; Value used to ; initialize data ; direction ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs 2010 Microchip Technology Inc. ...
Page 147
... Don’t care (TRIS bit does not affect port direction or is overridden for this option). TABLE 11-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 PORTJ RJ7 RJ6 LATJ LATJ Output Latch Register TRISJ PORTJ Data Direction Register 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output ...
Page 148
... One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pin has protection diodes to V Figure 11-4, PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Q RDx Pin TTL Read RD TTL Chip Select CS TTL Write WR TTL and 2010 Microchip Technology Inc. ...
Page 149
... General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 ...
Page 150
... TMR0IE INT0IE RBIE TMR0IF RC1IF TX1IF SSPIF CCP1IF RC1IE TX1IE SSPIE CCP1IE RC1IP TX1IP SSPIP CCP1IP Reset Bit 1 Bit 0 Values on Page RD1 RD0 RE1 RE0 — — — 65 INT0IF RBIF 63 TMR2IF TMR1IF 65 TMR2IE TMR1IE 65 TMR2IP TMR1IP 65 2010 Microchip Technology Inc. ...
Page 151
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 The T0CON register aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 152
... T Delay There is a delay between OSC Figure 12-2). TMR0H is updated with Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 153
... GIE/GIEH PEIE/GIEL TMR0IE T0CON TMR0ON T08BIT TRISA PORTA Data Direction Register Legend: Shaded cells are not used by Timer0. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
Page 154
... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 154 2010 Microchip Technology Inc. ...
Page 155
... Internal clock (F OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer1 module is shown in Figure operation in Read/Write mode is shown in The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation ...
Page 156
... Special Event Trigger Synchronize Detect 0 Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize Detect 0 Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
Page 157
... T1OSO See the Notes with Table 13-1 Note: information about capacitor selection. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 TABLE 13-1: Osc Type LP Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stabil- ity of the oscillator, but also increases the start-up time ...
Page 158
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine RTCinit. The Timer1 oscillator must also be enabled and running at all times. Section 16.3.4 Section 13.3 “Timer1 Oscillator”, 2010 Microchip Technology Inc. ...
Page 159
... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Initialize timekeeping registers ...
Page 160
... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 160 2010 Microchip Technology Inc. ...
Page 161
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 162
... RBIE TMR0IF TX1IF SSPIF CCP1IF TX1IE SSPIE CCP1IE TX1IP SSPIP CCP1IP Section 17.0 “Master Module”. Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 63 TMR2IF TMR1IF 65 TMR2IE TMR1IE 65 TMR2IP TMR1IP 2010 Microchip Technology Inc. ...
Page 163
... External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first falling edge Internal clock (F OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A simplified block diagram of the Timer3 module is shown in Figure operation in Read/Write mode is shown in The Timer3 module is controlled through the T3CON register ...
Page 164
... TMR3L TCCPx 1 Synchronize Detect 0 Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize Detect 0 Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR3L Write TMR3L 8 8 TMR3H 8 8 Internal Data Bus 2010 Microchip Technology Inc. ...
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... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 166 2010 Microchip Technology Inc. ...
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... Note 1: For CCP3, the Special Event Trigger is not available. This mode functions the same as Compare 2: Generate Interrupt mode (CCP3M<3:0> = 1010). 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Each CCP module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register ...
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... Timer3 is used for all Capture and Compare operations for all three CCP modules. Timer2 is used for PWM oper- ations for all three CCP modules. Timer1 is not used. All modules may share Timer2 and Timer3 resources as common time bases. 2010 Microchip Technology Inc. ...
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... CCP2CON<3:0> CCP2 Pin Prescaler Q1:Q4 CCP3CON<3:0> CCP3 Pin Prescaler 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 16.2.1 CCP PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRIS direction bit. If RC1/CCP2 or RE7/CCP2 is configured Note output, a write to the port can cause a capture condition ...
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... A/D conversion even when the A/D Converter is enabled. CCP3 is not equipped with a Special Event Trigger. Selecting the Compare Special Event Trigger mode for this device (CCP3M<3:0> = 1011) is functionally the same as selecting the Generate Software Interrupt mode (CCP3M<3:0> = 1010). 2010 Microchip Technology Inc. ...
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... FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM T3CCP2 0 1 T3CCP1 TMR1H TMR1L 0 TMR3H TMR3L 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Special Event Trigger (Timer1/Timer3 Reset) Set CCP1IF Compare Output Comparator Match Logic 4 CCPR1H CCPR1L CCP1CON<3:0> Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) ...
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... CCP3M2 CCP3M1 CCP3M0 Reset Bit 1 Bit 0 Values on Page INT0IF RBIF 63 PD POR BOR 64 TMR2IF TMR1IF 65 TMR2IE TMR1IE 65 TMR2IP TMR1IP 65 TMR3IF CCP2IF 65 TMR3IE CCP2IE 65 TMR3IP CCP2IP 65 — — CCP3IF 65 — — CCP3IE 65 — — CCP3IP TMR1CS TMR1ON TMR3CS TMR3ON 2010 Microchip Technology Inc. ...
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... PR2 Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 A PWM output and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period) ...
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... Timer2 by writing to T2CON. 5. Configure the CCP2 module for PWM operation. 9.77 kHz 39.06 kHz FFh FFh F OSC log --------------- F PWM = -----------------------------bits 2 log 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 2010 Microchip Technology Inc. ...
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... CCP2CON — — CCPR3L Capture/Compare/PWM Register 3 (LSB) CCPR3H Capture/Compare/PWM Register 3 (MSB) CCP3CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 Bit 5 Bit 4 Bit 3 TMR0IE INT0IE RBIE TMR0IF — RI ...
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... PIC18F6310/6410/8310/8410 NOTES: DS39635C-page 176 2010 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
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... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2010 Microchip Technology Inc. R-0 R bit Bit is unknown ...
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... In Master mode, the overflow bit is not set, since each new reception (and transmission) is initiated by Note 1: writing to the SSPBUF register. When enabled, these pins must be properly configured as inputs or outputs. 2: Bit combinations not specifically listed here are either reserved or implemented 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 R/W-0 R/W-0 R/W-0 (2) (3) ...
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... Example 17-1 loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. 2010 Microchip Technology Inc. shows the ...
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... SPI Master SSPM<3:0> = 00xxb Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 2 bit 5 bit 4 bit 3 bit 5 bit 4 bit 3 bit 2 17-3, Figure 17-5 and Figure 17- Clock Modes bit 1 bit 0 bit 1 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2 2010 Microchip Technology Inc. ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39635C-page 184 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2 2010 Microchip Technology Inc. ...
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... WCOL SSPOV SSPSTAT SMP CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 17.3.10 ...
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... SSPBUF and the SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. 2010 Microchip Technology Inc. ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by Note 1: writing to the SSPBUF register. When enabled, these pins must be properly configured as input or output. 2: Bit combinations not specifically listed here are either reserved or implemented 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C™ MODE) R-0 R-0 R-0 ...
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... Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle 3: mode. DS39635C-page 188 2 C™ MODE) R/W-0 R/W-0 R/W-0 (1) (1) D mode only) (3) R/W-0 R/W-0 R/W-0 (2,3) R bit 0 2010 Microchip Technology Inc. ...
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... Value that will be transmitted when the user initiates an Acknowledge sequence at the end of Note 1: a receive the I C module is not in Idle mode, this bit may not be set (no spooling) and the SSPBUF 2: may not be written (or writes to the SSPBUF are disabled). 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 2 C™ MODE) R/W-0 R/W-0 R/W-0 (1) ...
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... Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits, SSPIF and BF, are set). 9. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. 2010 Microchip Technology Inc. ...
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... The clock must be released by setting bit, CKP (SSPCON<4>). See Section 17.4.4 “Clock for more details. Stretching” 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F6310/6410/8310/8410 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39635C-page 192 2010 Microchip Technology Inc. ...
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... FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 193 ...
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... PIC18F6310/6410/8310/8410 2 FIGURE 17-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39635C-page 194 2010 Microchip Technology Inc. ...
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... FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 195 ...
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... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 17-11). 2010 Microchip Technology Inc. Figure 17-9). ...
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... SDA DX SCL CKP WR SSPCON 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the ...
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... PIC18F6310/6410/8310/8410 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39635C-page 198 2010 Microchip Technology Inc. ...
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... FIGURE 17-14: I C™ SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC18F6310/6410/8310/8410 DS39635C-page 199 ...
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... UA bit will not be set and the slave will begin receiving data after the Acknowledge (Figure Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read 17-15). Receiving Data ACK ‘0’ ‘1’ 2010 Microchip Technology Inc. ...