PIC18F6410-I/PT Microchip Technology, PIC18F6410-I/PT Datasheet - Page 90

• Manufacturer Part Number: PIC18F6410-I/PT
• Description: IC PIC MCU FLASH 8KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6410-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SPI/I2C/EUSART/AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

(TBLPTRU:TBLPTRH:TBLPTRL). Only the lower six
PIC18F6310/6410/8310/8410
7.2
Two control registers are used in conjunction with the
TBLRD and TBLWT instructions: the TABLAT register
and the TBLPTR register set.
7.2.1
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch register is used to
hold 8-bit data during data transfers between the
program memory space and data RAM.
7.2.2
The Table Pointer register (TBLPTR) addresses a byte
within the program memory. It is comprised of three
SFR registers: Table Pointer Upper Byte, Table Pointer
High
bits of TBLPTRU are used with TBLPTRH and TBLPTRL
to form a 22-bit wide pointer.
The contents of TBLPTR indicate a location in program
memory space. The low-order 21 bits allow the device
to address the full 2 Mbytes of program memory space.
The 22nd bit allows access to the configuration space,
including the device ID, user ID locations and the
Configuration bits.
The TBLPTR register set is updated when executing a
TBLRD or TBLWT operation in one of four ways, based
on the instruction’s arguments. These are detailed in
Table
the low-order 21 bits.
When a TBLRD or TBLWT is executed, all 22 bits of the
TBLPTR determine which address in the program
memory space is to be read or written to.
DS39635C-page 90
7-1. These operations on the TBLPTR only affect
Byte
Control Registers
TABLAT – TABLE LATCH REGISTER
TBLPTR – TABLE POINTER
REGISTER
and
Table
Pointer
Low
Byte
TABLE 7-1:
7.3
The TBLRD instruction is used to retrieve data from the
program memory space and places it into data RAM.
Table reads from program memory are performed one
byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word.
shows the interface between the internal program
memory and the TABLAT.
A typical method for reading data from program memory
is shown in
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
Example
TBLRD*
TBLWT*
Reading the Flash Program
Memory
Example
TBLPTR is not modified
TBLPTR is incremented after the
read/write
TBLPTR is decremented after the
read/write
TBLPTR is incremented before the
read/write
TABLE POINTER
OPERATIONS WITH TBLRD
AND TBLWT INSTRUCTIONS
Operation on Table Pointer
7-1.
 2010 Microchip Technology Inc.
Figure 7-2