DSPIC30F3010-30I/ML Microchip Technology, DSPIC30F3010-30I/ML Datasheet - Page 223

• Manufacturer Part Number: DSPIC30F3010-30I/ML
• Description: IC DSPIC MCU/DSP 24K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3010-30I/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Package: 44QFN EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 5
• For Use With: XLT44QFN4 - SOCKET TRANS ICE 28DIP TO 44QFNXLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F301030IML

Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics.
Timing Requirements
Timing Specifications
Trap Vectors ....................................................................... 46
© 2010 Microchip Technology Inc.
Dead Time .................................................................. 99
Edge-Aligned PWM..................................................... 97
External Clock........................................................... 172
I
I
Input Capture (CAPx)................................................ 183
Motor Control PWM Module...................................... 185
Motor Control PWM Module Fault............................. 185
OCx/PWM Module .................................................... 184
Oscillator Start-up Timer ........................................... 178
Output Compare Module........................................... 183
PWM Output ............................................................... 85
QEA/QEB Inputs ....................................................... 186
QEI Module Index Pulse ........................................... 187
Reset......................................................................... 178
SPI Module
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer1, 2, 3, 4, 5 External Clock............................... 180
TimerQ (QEI Module) External Clock ....................... 182
DC Characteristics - Internal RC Accuracy............... 175
A/D Conversion
Band Gap Start-up Time ........................................... 179
Brown-out Reset ....................................................... 178
CLKOUT and I/O....................................................... 177
External Clock........................................................... 173
I
I
Input Capture ............................................................ 183
Motor Control PWM Module...................................... 185
Oscillator Start-up Timer ........................................... 178
Output Compare Module........................................... 183
Power-up Timer ........................................................ 178
QEI Module
Quadrature Decoder ................................................. 186
Reset......................................................................... 178
Simple OCx/PWM Mode ........................................... 184
SPI Module
Timer1 External Clock............................................... 180
Timer3 and Timer5 External Clock ........................... 181
Watchdog Timer........................................................ 178
PLL Clock.................................................................. 174
2
2
2
2
C Bus Data
C Bus Start/Stop Bits
C Bus Data (Master Mode)..................................... 194
C Bus Data (Slave Mode)....................................... 195
Master Mode ..................................................... 193
Slave Mode ....................................................... 195
Master Mode ..................................................... 193
Slave Mode ....................................................... 195
Master Mode (CKE = 0) .................................... 188
Master Mode (CKE = 1) .................................... 189
Slave Mode (CKE = 1) ...................................... 191
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
10-Bit High-speed ............................................. 201
External Clock................................................... 182
Index Pulse ....................................................... 187
Master Mode (CKE = 0) .................................... 188
Master Mode (CKE = 1) .................................... 189
Slave Mode (CKE = 0) ...................................... 190
Slave Mode (CKE = 1) ...................................... 192
DD
).......................................... 142
DD
DD
), Case 1...................... 142
), Case 2...................... 142
U
UART
Unit ID Locations .............................................................. 135
Universal Asynchronous Receiver
W
Wake-up from Sleep ......................................................... 135
Wake-up from Sleep and Idle ............................................. 47
Watchdog Timer
Watchdog Timer (WDT)............................................ 135, 145
WWW Address ................................................................. 219
WWW, On-Line Support ....................................................... 7
dsPIC30F3010/3011
Address Detect Mode ............................................... 119
Auto Baud Support ................................................... 120
Baud Rate Generator ............................................... 119
Enabling and Setting Up UART ................................ 117
Loopback Mode ........................................................ 119
Module Overview...................................................... 115
Operation During CPU Sleep and Idle Modes.......... 120
Receiving Data ......................................................... 118
Reception Error Handling ......................................... 118
Transmitting Data ..................................................... 117
UART1 Register Map ............................................... 121
UART2 Register Map ............................................... 121
Transmitter Module (UART) ..................................... 115
Timing Characteristics .............................................. 178
Timing Requirements ............................................... 178
Enabling and Disabling............................................. 145
Operation.................................................................. 145
Alternate I/O ..................................................... 117
Disabling........................................................... 117
Enabling ........................................................... 117
Setting Up Data, Parity and Stop Bit Selections117
In 8-Bit or 9-Bit Data Mode ............................... 118
Interrupt ............................................................ 118
Receive Buffer (UxRXB)................................... 118
Framing Error (FERR) ...................................... 119
Idle Status ........................................................ 119
Parity Error (PERR) .......................................... 119
Receive Break .................................................. 119
Receive Buffer Overrun Error (OERR Bit) ........ 118
In 8-Bit Data Mode............................................ 117
In 9-Bit Data Mode............................................ 117
Interrupt ............................................................ 118
Transmit Buffer (UxTXB) .................................. 117
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