PIC24HJ64GP502-E/MM Microchip Technology, PIC24HJ64GP502-E/MM Datasheet - Page 105

IC PIC MCU FLASH 64K 28-QFN

PIC24HJ64GP502-E/MM

Manufacturer Part Number
PIC24HJ64GP502-E/MM
Description
IC PIC MCU FLASH 64K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP502-E/MM

Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit or 10-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164336 - MODULE SOCKET FOR PM3 28/44QFN
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
8.0
TABLE 8-1:
© 2011 Microchip Technology Inc.
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1 Data
OC1 – Output Compare 1 Secondary Data
IC2 – Input Capture 2
OC2 – Output Compare 2 Data
OC2 – Output Compare 2 Secondary Data
TMR2 – Timer2
TMR3 – Timer3
SPI1 – Transfer Done
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
ADC1 – ADC1 Convert Done
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
SPI2 – Transfer Done
ECAN1 – RX Data Ready
PMP – Master Data Transfer
ECAN1 – TX Data Request
Note 1: This data sheet summarizes the features
Peripheral to DMA Association
2: Some registers and associated bits
DIRECT MEMORY ACCESS
(DMA)
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04
of
PIC24HJ64GPX02/X04
PIC24HJ128GPX02/X04
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 38. “Direct Memory
Access (DMA) (Part III)” (DS70215) of
the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
the
PIC24HJ32GP302/304,
families
DMAxREQ Register
IRQSEL<6:0> Bits
and
of
in
0000000
0000001
0000010
0000010
0000101
0000110
0000110
0000111
0001000
0001010
0001011
0001100
0001101
0011110
0011111
0100001
0100010
0101101
1000110
Direct Memory Access (DMA) is a very efficient
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04
and PIC24HJ128GPX02/X04 peripherals that can
utilize DMA are listed in
Values to Read from
0x0300 (ADC1BUF0)
DMAxPAD Register
0x0226 (U1RXREG)
0x0236 (U2RXREG)
intervention.
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0608 (PMDIN1)
0x0140 (IC1BUF)
0x0144 (IC2BUF)
0x0440 (C1RXD)
Peripheral
The
Table
DMA
8-1.
DMAxPAD Register
0x0224 (U1TXREG)
0x0234 (U2TXREG)
Values to Write to
0x0248 (SPI1BUF)
0x0268 (SPI2BUF)
0x0608 (PMDIN1)
0x0180 (OC1RS)
0x0186 (OC2RS)
0x0442 (C1TXD)
0x0182 (OC1R)
0x0188 (OC2R)
DS70293E-page 105
Peripheral
controller
can

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