PIC16F876-20/SO Microchip Technology, PIC16F876-20/SO Datasheet - Page 83

• Manufacturer Part Number: PIC16F876-20/SO
• Description: IC MCU FLASH 8KX14 EE 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876-20/SO

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP, PSP, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 5 Channel
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Data Rom Size: 256 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 5
• Height: 2.31 mm
• Length: 17.87 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.10
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I
module is in the IDLE state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the baud rate generator is loaded with the
contents of SSPADD<6:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (T
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled high
the baud rate generator is reloaded with the contents of
SSPADD<6:0> and begins counting. SDA and SCL
must be sampled high for one T
followed by assertion of the SDA pin (SDA is low) for
one T
bit in the SSPCON2 register will be automatically
cleared and the baud rate generator will not be
reloaded, leaving the SDA pin held low. As soon as a
START condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
not be set until the baud rate generator has timed out.
FIGURE 9-13:
Note 1: If RSEN is programmed while any other
2001 Microchip Technology Inc.
BRG
2: A bus collision during the Repeated
, while SCL is high. Following this, the RSEN
I
START CONDITION TIMING
event is in progress, it will not take effect.
2
•
START condition occurs if:
• SDA is sampled low when SCL
C MASTER MODE REPEATED
Falling edge of ninth clock
goes from low to high.
SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
BRG
). When the baud rate generator
REPEAT START CONDITION WAVEFORM
SDA
SCL
End of Xmit
BRG
Write to SSPCON2
occurs here
SDA = 1,
SCL (no change)
. This action is then
2
C
T
SDA = 1,
SCL = 1
BRG
T
BRG
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
9.2.10.1
If the user writes the SSPBUF when a Repeated
START sequence is in progress, then WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note:
Sr = Repeated START
T
BRG
At completion of START bit,
hardware clears RSEN bit
Set S (SSPSTAT<3>)
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
and sets SSPIF
Write to SSPBUF occurs here
T
WCOL Status Flag
BRG
1st bit
T
BRG
PIC16F87X
DS30292C-page 81