AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 134

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

15.4.2
15.4.3
15.5
15.5.1
15.5.1.1
15.5.2
32015G–AVR32–09/09
Functional Description
Power Management
Interrupt
External Interrupts
NMI Control
Synchronization of external interrupts
Edge triggered interrupts are available in all sleep modes except Deepdown. Level triggered
interrupts and the NMI interrupt are available in all sleep modes.
The EIC interrupt lines are connected to internal sources of the interrupt controller. Using the
External Interrutps requires the interrupt controller to be programmed first.
Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.
Each external interrupt pin EXTINTn can be configured to produce an interrupt on rising or fall-
ing edge, or high or low level. External interrupts are configured by the MODE, EDGE, and
LEVEL registers. Each interrupt n has a bit INTn in each of these registers.
Similarly, each interrupt has a corresponding bit in each of the interrupt control and status regis-
ters. Writing 1 to the INTn strobe in IER enables the external interrupt on pin EXTINTn, while
writing 1 to INTn in IDR disables the external interrupt. IMR can be read to check which inter-
rupts are enabled. When the interrupt triggers, the corresponding bit in ISR will be set. For edge
triggered interrupts, the flag remains set until the corresponding strobe bit in ICR is written to 1.
For level triggered interrupts, the flag remains set for as long as the interrupt condition is present
on the pin.
Writing INTn in MODE to 0 enables edge triggered interrupts, while writing the bit to 1 enables
level triggered interrupts.
If EXTINTn is configured as an edge triggered interrupt, writing INTn in EDGE to 0 will trigger the
interrupt on falling edge, while writing the bit to 1 will trigger the interrupt on rising edge.
If EXTINTn is configured as a level triggered interrupt, writing INTn in LEVEL to 0 will trigger the
interrupt on low level, while writing the bit to 1 will trigger the interrupt on high level.
The pin value of the EXTINTn pins is normally synchronized to the CPU clock, so spikes shorter
than a CPU clock cycle are not guaranteed to produce an interrupt. In Stop mode, spikes shorter
than a 32KHz clock cycle are not guaranteed to produce an interrupt. In Deepdown mode, only
unsynchronized level interrupts remain active, and any short spike on this interrupt will wake up
the device.
The Non-Maskable Interrupt of the CPU is connected to the NMI_N pin through masking logic in
the External Interrupt Controller. This masking ensures that the NMI will not trigger before the
CPU has been set up to handle interrupts. Writing the EN bit in the NMIC register enables the
NMI interrupt, while writing EN to 0 disables the NMI interrupt. When enabled, the interrupt trig-
gers whenever the NMI_N pin is negated.
The NMI_N pin is synchronized the same way as external level interrupts.
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