AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 54

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

PICOSVMUL – PICO Single Vector Multiplication
Description
Performs three vector multiplications where the input pixels taken from the INPIXn registers depends on the Input Selection
Mode and the input pixel addresses given in the instruction. The results from each Vector Multiplication Unit (VMU) are then
added together for one of the outputs to the Output Pixels Inserter to form the result of a single vector multiplication of two
9-element vectors. The results from the VMUs are then scaled and saturated to unsigned 8-bit values before being inserted
into the OUTPIXn registers. Which pixels to update in the OUTPIXn registers depend upon the Output Insertion Mode and
the output pixel address given in the instruction.
Operation:
I.
32015G–AVR32–09/09
OFFSET_SCALE = COEFF_FRAC_BITS - OFFSET_FRAC_BITS
if ( Input Selection Mode == Horizontal Filter Mode ) then
else if ( Input Selection Mode == Vertical Filter Mode ) then
else if ( Input Selection Mode == Transformation Mode ) then
if ( Output Insertion Mode == Packed Insertion Mode ) then
else if ( Output Insertion Mode == Planar Insertion Mode ) then
VMU0_OUT
VMU1_OUT
VMU2_OUT
VMU0_OUT
VMU1_OUT
VMU2_OUT
OUT(d*3 + 0) ← SATSU(ASR(VMU0_OUT + VMU1_OUT + VMU2_OUT, COEFF_FRAC_BITS), 8);
OUT(d*3 + 1) ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);
OUT(d*3 + 2) ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);
OUT(d + 0) ← SATSU(ASR(VMU0_OUT + VMU1_OUT+ VMU2_OUT, COEFF_FRAC_BITS), 8);
OUT(d + 4) ← SATSU(ASR(VMU1_OUT, COEFF_FRAC_BITS), 8);
OUT(d + 8) ← SATSU(ASR(VMU2_OUT, COEFF_FRAC_BITS), 8);
VMU0_OUT
VMU1_OUT
VMU2_OUT
=
=
=
=
=
=
=
COEFF0_0 COEFF0_1 COEFF0_2
COEFF1_0 COEFF1_1 COEFF1_2
COEFF2_0 COEFF2_1 COEFF2_2
COEFF0_0 COEFF0_1 COEFF0_2
COEFF1_0 COEFF1_1 COEFF1_2
COEFF2_0 COEFF2_1 COEFF2_2
COEFF0_0 COEFF0_1 COEFF0_2
COEFF1_0 COEFF1_1 COEFF1_2
COEFF2_0 COEFF2_1 COEFF2_2
IN((x+0)%11)
IN((x+4)%11)
IN((x+8)%11)
IN((y+0)%11)
IN((y+4)%11)
IN((y+8)%11)
IN((z+0)%11)
IN((z+4)%11)
IN((z+8)%11)
IN(x+0)
IN(x+1)
IN(x+2)
IN(y+0)
IN(y+1)
IN(y+2)
IN(z+0)
IN(z+1)
IN(z+2)
INx
INy
INz
+
OFFSET0 << OFFSET_SCALE
OFFSET1 << OFFSET_SCALE
OFFSE20 << OFFSET_SCALE
+
+
+
OFFSET0 << OFFSET_SCALE
OFFSET1 << OFFSET_SCALE
OFFSET2 << OFFSET_SCALE
+
+
+
OFFSET0 << OFFSET_SCALE
OFFSET1 << OFFSET_SCALE
OFFSET2 << OFFSET_SCALE
AT32AP7001
54