AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 500

IC MCU 32BIT AVR32 208-LQFP

AT32AP7001-ALUT

Manufacturer Part Number
AT32AP7001-ALUT
Description
IC MCU 32BIT AVR32 208-LQFP
Manufacturer
Atmel
Series
AVR®32 AP7r
Datasheets

Specifications of AT32AP7001-ALUT

Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, POR, PWM, WDT
Number Of I /o
90
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
EBI, ISI, MCI, PS2, SPI, TWI, USB
Maximum Clock Frequency
150 MHz
Number Of Programmable I/os
90
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 1 Channel
Package
208PQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32AP7001-ALUT
Manufacturer:
EVERLIGHT
Quantity:
12 000
Part Number:
AT32AP7001-ALUT
Manufacturer:
Atmel
Quantity:
10 000
32015G–AVR32–09/09
•Write cycle
Figure 28-13. Write Cycle
The write cycle time is defined as the total duration of the write cycle, that is, from the time where
address is set on the address bus to the point where address may change. The total write cycle
time is equal to:
Similarly,
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of CLK_SMC cycles. To ensure that the NWE and NCS timings are coherent, the user must
define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time
and NCS (write) hold times as:
And,
NBS0, NBS1,
A0, A1
CLK_SMC
A[25:2]
NWECYCLE
NCSWRHOLD
NWE
NCS
NWECYCLE
NWEHOLD
NCSWRSETUP
NWESETUP
=
=
NCSWRSETUP
=
=
NWECYCLE NCSWRSETUP
NWECYCLE NWESETUP
NWESETUP
NCSWRPULSE
NWECYCLE
NWEPULSE
+
+
NCSWRPULSE
NWEPULSE
+
NWEHOLD
NWEPULSE
+
NWEHOLD
NCSWRPULSE
NCSWRHOLD
AT32AP7001
NCSWRHOLD
500

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