PIC16C771/JW Microchip Technology, PIC16C771/JW Datasheet - Page 14

• Manufacturer Part Number: PIC16C771/JW
• Description: IC MCU EPROM4KX14 A/D PWM 20CDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C771/JW

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: EPROM, UV
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-CDIP (0.300", 7.62mm) Window
• For Use With: ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Q1066306

PIC16C717/770/771
TABLE 2-1:
DS41120B-page 12
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
Address Name
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Bank 1
(3)
(3)
(3)
(3)
(1,3)
(3)
2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from any bank.
OPTION_REG
P1DEL
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
INDF
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
WPUB
IOCB
REFCON
LVDCON
ANSEL
ADRESL
ADCON1
—
—
—
—
—
—
—
—
PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTA Data Direction Register
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
PORTB Weak Pull-up Control
PORTB Interrupt on Change Control
PWM 1 Delay value
Unimplemented
Unimplemented
Unimplemented
A/D Low Byte Result Register
VRHEN
GCEN
RBPU
LVDIE
ADFM
Bit 7
SMP
IRP
GIE
—
—
—
—
—
ACKSTAT
INTEDG
VCFG2
VRLEN
ADIE
Bit 6
PEIE
CKE
RP1
—
—
—
—
—
Analog Channel Select
VRHOEN
2
ACKDT
VCFG1
C mode) Address Register
BGST
T0CS
Bit 5
T0IE
RP0
D/A
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
VRLOEN
ACKEN
VCFG0
LVDEN
T0SE
Bit 4
INTE
TO
—
—
—
P
SSPIE
BCLIE
OSCF
RCEN
RBIE
LVV3
Bit 3
PSA
PD
—
—
S
CCP1IE
LVV2
Bit 2
T0IF
PEN
R/W
PS2
—
—
—
—
Z
TMR2IE
RSEN
LVV1
Bit 1
INTF
POR
PS1
DC
UA
—
—
—
2002 Microchip Technology Inc.
TMR1IE
RBIF
LVV0
Bit 0
BOR
PS0
SEN
BF
—
—
—
C
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
---0 0000
0000 000x
-0-- 0000
0--- 0---
---- 1-qq
0000 0000
1111 1111
0000 0000
0000 0000
1111 1111
1111 0000
0000 0000
0000 ----
--00 0101
--11 1111
xxxx xxxx
0000 ----
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
Details
Page:
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101
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on
23
15
22
14
23
25
33
22
16
17
19
21
69
52
76
66
34
34
62
25
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