P87LPC762FD,512 NXP Semiconductors, P87LPC762FD,512 Datasheet - Page 29

• Manufacturer Part Number: P87LPC762FD,512
• Description: IC 80C51 MCU 2K OTP 20-SOIC
• Manufacturer: NXP Semiconductors
• Series: LPC700r

Specifications of P87LPC762FD,512

• Program Memory Type: OTP
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, WDT
• Number Of I /o: 18
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P87LPC7x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 45 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM10063 - PROGRAMMER LPC700 P76XLCPOM10050 - EMULATOR LPC700 PDS76X
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3212-5; 935266853512; P87LPC762FD

Philips Semiconductors
Table 8. Sources of Wakeup from Power Down Mode
2001 Oct 26
Wakeup Source
External Interrupt 0 or 1
Keyboard Interrupt
Comparator 1 or 2
Watchdog Timer Reset
Watchdog Timer Interrupt
Brownout Detect Reset
Brownout Detect Interrupt
Reset Input
Low power, low price, low pin count (20 pin)
microcontroller with 2 kbyte OTP
Conditions
The corresponding interrupt must be enabled.
The keyboard interrupt feature must be enabled and properly set up. The corresponding interrupt must be
enabled.
The comparator(s) must be enabled and properly set up. The corresponding interrupt must be enabled.
The watchdog timer must be enabled via the WDTE bit in the UCFG1 EPROM configuration byte.
The WDTE bit in the UCFG1 EPROM configuration byte must not be set. The corresponding interrupt must
be enabled.
The BOD bit in AUXR1 must not be set (brownout detect not disabled). The BOI bit in AUXR1 must not be
set (brownout interrupt disabled).
The BOD bit in AUXR1 must not be set (brownout detect not disabled). The BOI bit in AUXR1 must be set
(brownout interrupt enabled). The corresponding interrupt must be enabled.
The external reset input must be enabled.
26
87LPC762
Preliminary data