IC ARM7 MCU FLASH 32K 48-LQFP

LPC2103FBD48,151

Manufacturer Part NumberLPC2103FBD48,151
DescriptionIC ARM7 MCU FLASH 32K 48-LQFP
ManufacturerNXP Semiconductors
SeriesLPC2100
LPC2103FBD48,151 datasheet
 


Specifications of LPC2103FBD48,151

Program Memory TypeFLASHProgram Memory Size32KB (32K x 8)
Package / Case48-LQFPCore ProcessorARM7
Core Size16/32-BitSpeed70MHz
ConnectivityI²C, Microwire, SPI, SSI, SSP, UART/USARTPeripheralsPOR, PWM, WDT
Number Of I /o32Ram Size8K x 8
Voltage - Supply (vcc/vdd)1.65 V ~ 3.6 VData ConvertersA/D 8x10b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Processor SeriesLPC21CoreARM7TDMI-S
Data Bus Width16 bit, 32 bitData Ram Size8 KB
Interface TypeI2C/JTAG/SPI/SSP/UARTMaximum Clock Frequency70 MHz
Number Of Programmable I/os32Number Of Timers4
Operating Supply Voltage3.3 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT3rd Party Development ToolsMDK-ARM, RL-ARM, ULINK2, DB-LQFP48-LPC2103, MCB2103, MCB2103U, MCB2103UME, KSK-LPC2103-01, KSK-LPC2103-01PL, KSK-LPC2103-02
Development Tools By SupplierOM10079, OM10081, OM10090Minimum Operating Temperature- 40 C
On-chip Adc8-ch x 10-bitCpu FamilyLPC2000
Device CoreARM7TDMI-SDevice Core Size16/32Bit
Frequency (max)70MHzTotal Internal Ram Size8KB
# I/os (max)32Number Of Timers - General Purpose4
Operating Supply Voltage (typ)1.8/3.3VOperating Supply Voltage (max)1.95/3.6V
Operating Supply Voltage (min)1.65/3VInstruction Set ArchitectureRISC
Operating Temp Range-40C to 85COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count48
Package TypeLQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
For Use With568-4310 - EVAL BOARD LPC2158 W/LCD568-4302 - BOARD EVAL LPC210X KS2103 JLINK568-4301 - BOARD EVAL LPC210X KS2103568-4300 - BOARD EVAL LPC210X MCB2103568-4297 - BOARD EVAL LPC21XX MCB2100MCB2103UME - BOARD EVAL MCB2103 + ULINK-MEMCB2103U - BOARD EVAL MCB2103 + ULINK2622-1013 - BOARD FOR LPC2103 48-LQFP622-1008 - BOARD FOR LPC9103 10-HVSONMCB2103 - BOARD EVAL NXP LPC2101/2101/2103622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2KEeprom Size-
Other names568-2094
935280966151
LPC2103FBD48-S
  
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LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB
flash with ISP/IAP, fast ports and 10-bit ADC
Rev. 04 — 2 June 2009
1. General description
The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with
real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
Due to their tiny size and low power consumption, the LPC2101/02/03 are ideal for
applications where miniaturization is a key requirement. A blend of serial communications
interfaces ranging from multiple UARTs, SPI to SSP and two I
on-chip SRAM of 2 kB/4 kB/8 kB, make these devices very well suited for communication
gateways and protocol converters. The superior performance also makes these devices
suitable for use as math coprocessors. Various 32-bit and 16-bit timers, an improved
10-bit ADC, PWM features through output match on all timers, and 32 fast GPIO lines with
up to nine edge or level sensitive external interrupt pins make these microcontrollers
particularly suitable for industrial control and medical systems.
2. Features
2.1 Enhanced features
Enhanced features are available in parts LPC2101/02/03 labelled Revision A and higher:
I
Deep power-down mode with option to retain SRAM memory and/or RTC.
I
Three levels of flash Code Read Protection (CRP) implemented.
2.2 Key features
I
16-bit/32-bit ARM7TDMI-S microcontroller in tiny LQFP48 and HVQFN48 packages.
I
2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program
memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.
I
ISP/IAP via on-chip bootloader software. Single flash sector or full chip erase in
100 ms and programming of 256 bytes in 1 ms.
I
EmbeddedICE-RT offers real-time debugging with the on-chip RealMonitor software.
I
The 10-bit ADC provides eight analog inputs, with conversion times as low as 2.44 s
per channel and dedicated result registers to minimize interrupt overhead.
I
Two 32-bit timers/external event counters with combined seven capture and seven
compare channels.
Product data sheet
2
C-buses, combined with

LPC2103FBD48,151 Summary of contents

  • Page 1

    LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers; 8 kB/16 kB/32 kB flash with ISP/IAP, fast ports and 10-bit ADC Rev. 04 — 2 June 2009 1. General description The LPC2101/02/03 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines ...

  • Page 2

    ... NXP Semiconductors I Two 16-bit timers/external event counters with combined three capture and seven compare channels. I Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock input. I Multiple serial interfaces including two UARTs (16C550), two Fast I (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. ...

  • Page 3

    ... NXP Semiconductors 4. Block diagram LPC2101/2102/2103 HIGH SPEED P0[31:0] GENERAL PURPOSE I/O BOOT ROM ARM7 local bus INTERNAL SRAM CONTROLLER 2 kB/4 kB SRAM EINT2 to EXTERNAL (1) EINT0 INTERRUPTS (1) 3 CAP0 (1) 4 CAP1 CAPTURE/COMPARE (1) 3 CAP2 EXTERNAL COUNTER (1) 3 MAT0 TIMER 0/TIMER 1/ (1) 4 MAT1 TIMER 2/TIMER 3 ...

  • Page 4

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 P0.27/TRST/CAP2.0 P0.28/TMS/CAP2.1 P0.29/TCK/CAP2.2 Fig 2. LPC2101_02_03_4 Product data sheet VBAT 5 V DD(1V8) LPC2101FBD48 RST 6 LPC2102FBD48 V 7 LPC2103FBD48 XTAL1 12 XTAL2 Pin configuration (LQFP48) Rev. 04 — 2 June 2009 LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers 36 P0.11/CTS1/CAP1.1/AD0.4 35 P0.10/RTS1/CAP1.0/AD0 ...

  • Page 5

    ... NXP Semiconductors P0.19/MAT1.2/MISO1 P0.20/MAT1.3/MOSI1 P0.21/SSEL1/MAT3.0 P0.27/TRST/CAP2.0 Fig 3. LPC2101_02_03_4 Product data sheet terminal 1 index area VBAT DD(1V8) LPC2102FHN48 6 RST LPC2103FHN48 LPC2103FHN48H 8 P0.28/TMS/CAP2 P0.29/TCK/CAP2.2 XTAL1 11 XTAL2 12 Transparent top view Pin configuration (HVQFN48) Rev. 04 — 2 June 2009 LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers 36 P0.11/CTS1/CAP1.1/AD0.4 35 P0.10/RTS1/CAP1.0/AD0 ...

  • Page 6

    ... NXP Semiconductors 5.2 Pin description Table 3. Pin description Symbol Pin P0.0 to P0.31 [1] P0.0/TXD0/ 13 MAT3.1 [1] P0.1/RXD0/ 14 MAT3.2 [2] P0.2/SCL0/ 18 CAP0.0 [2] P0.3/SDA0/ 21 MAT0.0 [1] P0.4/SCK0/ 22 CAP0.1 [1] P0.5/MISO0/ 23 MAT0.1 [1] P0.6/MOSI0/ 24 CAP0.2 [1] P0.7/SSEL0/ 28 MAT2.0 [1] P0.8/TXD1/ 29 MAT2.1 [1] P0.9/RXD1/ 30 MAT2.2 [3] P0.10/RTS1/ 35 CAP1.0/AD0.3 LPC2101_02_03_4 Product data sheet Type Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit ...

  • Page 7

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [3] P0.11/CTS1/ 36 CAP1.1/AD0.4 [3] P0.12/DSR1/ 37 MAT1.0/AD0.5 [1] P0.13/DTR1/ 41 MAT1.1 [4][5] P0.14/DCD1/ 44 SCK1/EINT1 [4] P0.15/RI1/ 45 EINT2 [4] P0.16/EINT0/ 46 MAT0.2 [6] P0.17/CAP1.2/ 47 SCL1 [6] P0.18/CAP1.3/ 48 SDA1 [1] P0.19/MAT1.2/ 1 MISO1 [1] P0.20/MAT1.3/ 2 MOSI1 [1] P0.21/SSEL1/ 3 MAT3.0 LPC2101_02_03_4 Product data sheet Type Description I/O P0.11 — General purpose input/output digital pin. ...

  • Page 8

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin [3] P0.22/AD0.0 32 [3] P0.23/AD0.1 33 [3] P0.24/AD0.2 34 [3] P0.25/AD0.6 38 [3] P0.26/AD0.7 39 [1] P0.27/TRST/ 8 CAP2.0 [1] P0.28/TMS/ 9 CAP2.1 [1] P0.29/TCK/ 10 CAP2.2 [1] P0.30/TDI/ 15 MAT3.3 [1] P0.31/TDO 16 [7][8] RTCX1 20 [7][8] RTCX2 25 [7] RTCK 26 XTAL1 11 XTAL2 12 DBGSEL 27 RST 6 LPC2101_02_03_4 Product data sheet ...

  • Page 9

    ... NXP Semiconductors Table 3. Pin description …continued Symbol Pin SSA V 42 DDA V 5 DD(1V8) V 17, 40 DD(3V3) VBAT 4 [ tolerant (if V and V DD(3V3) DDA [2] Open-drain 5 V tolerant (if V DD(3V3) pull-up to provide an output functionality. Open-drain configuration applies to ALL functions on that pin. [ tolerant (if V and V ...

  • Page 10

    ... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC) ...

  • Page 11

    ... NXP Semiconductors 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2101/02/03 provide 2 kB static RAM. 6.4 Memory map The LPC2101/02/03 memory map incorporates several distinct regions, as shown in Figure 4 ...

  • Page 12

    ... NXP Semiconductors 6.5 Interrupt controller The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. ...

  • Page 13

    ... NXP Semiconductors 6.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins ...

  • Page 14

    ... NXP Semiconductors • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. • UART1 is equipped with standard modem interface signals. This module also provides full support for hardware fl ...

  • Page 15

    ... NXP Semiconductors • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. 6.12 SSP serial I/O controller The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus ...

  • Page 16

    ... NXP Semiconductors – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.14 General purpose 16-bit timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt ...

  • Page 17

    ... NXP Semiconductors • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (T T PCLK 6.16 Real-time clock The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected ...

  • Page 18

    ... NXP Semiconductors 6.17.3 Reset and wake-up timer Reset has two sources on the LPC2101/02/03: the RST pin and watchdog reset. The RST pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fi ...

  • Page 19

    ... NXP Semiconductors 6.17.4 Code security (Code Read Protection - CRP) This feature of the LPC2101/02/03 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...

  • Page 20

    ... NXP Semiconductors In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. ...

  • Page 21

    ... NXP Semiconductors 6.18.1 EmbeddedICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the remote debug protocol commands to the JTAG data needed to access the ARM core. ...

  • Page 22

    ... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V analog input voltage IA V input voltage ...

  • Page 23

    ... NXP Semiconductors 8. Static characteristics Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage DD(1V8) (1 supply voltage DD(3V3) (3 analog 3.3 V pad DDA supply voltage V input voltage on pin i(VBAT) VBAT Standard port pins, RST, RTCK I LOW-level input ...

  • Page 24

    ... NXP Semiconductors Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I pull-up current pu I core supply current DD(CORE) I battery supply BAT current 2 I C-bus pins V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys V LOW-level output ...

  • Page 25

    ... NXP Semiconductors Table 5. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V output voltage on o(XTAL2) pin XTAL2 V input voltage on pin i(RTCX1) RTCX1 V output voltage on o(RTCX2) pin RTCX2 [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...

  • Page 26

    ... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 5. ADC conversion characteristics LPC2101_02_03_4 ...

  • Page 27

    ... NXP Semiconductors 8.1 Power consumption in Deep power-down mode I DD(CORE Fig 6. I BAT ( A Fig 7. LPC2101_02_03_4 Product data sheet 1.5 1.25 1 0.75 0 Test conditions: Deep power-down mode entered; RTC off; SRAM off 3.3 V. i(VBAT) DD(3V3) DDA Core supply current I measured at different temperatures and supply ...

  • Page 28

    ... NXP Semiconductors I DD(IO Fig 8. LPC2101_02_03_4 Product data sheet 0.20 0.15 0.10 0. Test conditions: Deep power-down mode entered; RTC off; SRAM off 1 3.3 V. DD(1V8) i(BAT) DDA I/O supply current I measured at different temperatures DD(IO) Rev. 04 — 2 June 2009 LPC2101/02/03 Single-chip 16-bit/32-bit microcontrollers 002aae682 ...

  • Page 29

    ... NXP Semiconductors 9. Dynamic characteristics Table 7. Dynamic characteristics for commercial applications +85 C for industrial applications, V amb [1] specified ranges . Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time CLCH ...

  • Page 30

    ... NXP Semiconductors 10.2 XTAL and RTC Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C case of third overtone crystal usage, have a common ground plane. The external components must also be connected to the ground plain ...

  • Page 31

    ... NXP Semiconductors 11. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...

  • Page 32

    ... NXP Semiconductors HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included ...

  • Page 33

    ... NXP Semiconductors HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0. 0.2 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included ...

  • Page 34

    ... NXP Semiconductors 12. Abbreviations Table 8. Acronym ADC AMBA APB DCC DSP FIFO FIQ GPIO IAP IRQ ISP PLL PWM SPI SRAM SSI SSP TTL UART VIC LPC2101_02_03_4 Product data sheet Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus ...

  • Page 35

    ... NXP Semiconductors 13. Revision history Table 9. Revision history Document ID Release date LPC2101_02_03_4 20090602 • Modifications: Section 6.17.4 “Code security (Code Read Protection - CRP levels (applicable to Revision A and higher). • Section 6.17.7 “Power Revision A and higher). • Section 10.1 “XTAL1 input” ...

  • Page 36

    ... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

  • Page 37

    ... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Enhanced features . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Functional description . . . . . . . . . . . . . . . . . . 10 6.1 Architectural overview 6.2 On-chip flash program memory . . . . . . . . . . . 10 6 ...