P80C552IBA/08,512 NXP Semiconductors, P80C552IBA/08,512 Datasheet - Page 20

• Manufacturer Part Number: P80C552IBA/08,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C552IBA/08,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 24MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 256Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1238-5; 935262804512; P80C552IBA

1. Active Mode:
2. Idle Mode:
3. Power Down Mode:
Philips Semiconductors
NOTES:
2002 Sep 03
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
a. The following pins must be forced to V
b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
a. The following pins must be forced to V
b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
a. The following pins must be forced to V
b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
CLOCK SIGNAL
exceed the I
exceed the I
exceed the I
CLOCK SIGNAL
Figure 12. I
Figure 13. I
(NC)
All other pins are disconnected
(NC)
All other pins are disconnected
V
OL1
OL1
OL1
DD
V
V
DD
DD
spec of these pins.
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
DD
DD
P1.6
P1.7
RST
STADC
XTAL2
XTAL1
V
Test Condition, Active Mode
SS
Test Condition, Idle Mode
P1.6
P1.7
RST
XTAL2
XTAL1
V
STADC
SS
AV
AV
V
ref–
DD
SS
DD
SS
DD
SS
DD
EW
P0
SS
EA
AV
AV
V
: STADC, AV
: RST, STADC, AV
: RST, STADC, XTAL1, AV
ref–
: EA, RST, Port 0, and EW.
: Port 0 and EW.
: Port 0 and EW.
DD
EW
EA
SS
P0
DD
DD
DD
1
2
I
DD
through resistors of sufficiently high value such that the sink current into these pins cannot
through resistors of sufficiently high value such that the sink current into these pins cannot
through resistors of sufficiently high value such that the sink current into these pins cannot
V
I
DD
DD
SU01704
SU01705
V
DD
V
DD
ss
V
DD
, and AV
ss
,, AV
20
ref–
ref–
.
ss
, and EA.
,, AV
Figure 14. Clock Signal Waveform for I
ref–
All other pins are disconnected. V
V
Figure 15. I
DD
, and EA.
0.5 V
–0.5
(NC)
Idle Modes t
V
DD
DD
0.2V
t
CHCL
0.7V
Test Condition, Power Down Mode
DD
DD
–0.1
P1.6
P1.7
RST
STADC
XTAL2
XTAL1
V
SS
CLCH
t
CLCX
= t
80C552/83C552
CHCL
t
CLCL
DD
DD
AV
AV
= 5ns
V
ref–
DD
Tests in Active and
EW
= 2 V to 5.5 V
EA
SS
P0
t
CHCX
t
CLCH
I
DD
SU01706
V
SU01707
Product data
DD
V
3
DD