P80C552IBA/08,512 NXP Semiconductors, P80C552IBA/08,512 Datasheet - Page 8

• Manufacturer Part Number: P80C552IBA/08,512
• Description: IC 80C51 MCU 8BIT ROMLESS 68PLCC
• Manufacturer: NXP Semiconductors
• Series: 80Cr

Specifications of P80C552IBA/08,512

• Program Memory Type: ROMless
• Package / Case: 68-PLCC
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 40
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Processor Series: P80C5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C/UART
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: 0 C
• On-chip Adc: 8-ch x 10-bit
• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 24MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 256Byte
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 68
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1238-5; 935262804512; P80C552IBA

1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V
Philips Semiconductors
PIN DESCRIPTION (Continued)
NOTE:
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol, page 2.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
IDLE MODE
In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
Table 1. External Pin Status During Idle and Power-Down Modes
2002 Sep 03
V
PSEN
ALE
EA
AV
AV
AV
AV
DD
MNEMONIC
SS
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
Idle
Idle
Power-down
Power-down
respectively.
REF–
REF+
SS
DD
and RST must come up at the same time for a proper start-up.
MODE
PLCC
36, 37
47
48
49
58
59
60
61
PROGRAM
MEMORY
PIN NO.
External
External
Internal
Internal
34-36
QFP
48
49
50
59
60
61
63
TYPE
ALE
O
O
1
1
0
0
I
I
I
I
I
I
Two Digital ground pins.
Program Store Enable: Active-low read strobe to external program memory.
Address Latch Enable: Latches the low byte of the address during accesses to external
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up.
External Access: When EA is held at TTL level high, the CPU executes out of the internal
program ROM provided the program counter is less than 8192. When EA is held at TTL
low level, the CPU executes out of external program memory. EA is not allowed to float.
Analog to Digital Conversion Reference Resistor: Low-end.
Analog to Digital Conversion Reference Resistor: High-end.
Analog Ground
Analog Power Supply
PSEN
1
1
0
0
PORT 0
Data
Float
Data
Float
8
reset is the only way to terminate the power-down mode. The control
protected and cannot be read out at any time by any test mode or by
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.
ROM CODE PROTECTION (83C552)
The 83C552 has an additional security feature. ROM code
protection may be selected by setting a mask–programmable
security bit (i.e., user dependent). This feature may be requested
during ROM code submission. When selected, the ROM code is
any instruction in the external program memory space.
The MOVC instructions are the only instructions that have access to
program code in the internal or external program memory. The EA
input is latched during RESET and is “don’t care” after RESET
(also if the security bit is not set). This implementation prevents
reading internal program code by switching from external program
memory to internal program memory during a MOVC instruction or
any other instruction that uses immediate data.
PORT 1
Data
Data
Data
Data
NAME AND FUNCTION
Address
PORT 2
Data
Data
Data
PORT 3
Data
Data
Data
Data
DD
80C552/83C552
+ 0.5 V or V
PORT 4
Data
Data
Data
Data
SS
– 0.5 V,
Product data
PWM0/
PWM1
1
1
1
1