Z8F6422VS020SG Zilog, Z8F6422VS020SG Datasheet - Page 246

• Manufacturer Part Number: Z8F6422VS020SG
• Description: IC ENCORE MCU FLASH 64K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F6422VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F642x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F64200100KITG, Z8F64230100ZDF, ZENETSC0100ZACG, ZUSBOPTSC01ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4678 - KIT DEV FOR Z8F642 MCU 44 PIN269-4677 - KIT DEV FOR Z8F642 MCU 28PIN269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN269-4540 - KIT DEV FOR Z8 ENCORE 16K TO 64K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4285; Z8F6422VS020SG

PS019921-0308
(Output)
(Input)
(Input)
MISO
MOSI
SCK
SPI Slave Mode Timing
SS
Figure 53
is shown with SCK rising edge used to source MISO output data, SCK falling edge used to
sample MOSI input data.
Table 118. SPI Slave Mode Timing
Parameter
SPI Slave
T
T
T
T
T4
1
2
3
4
T1
and
Abbreviation
SCK (transmit edge) to MISO output Valid Delay
MOSI input to SCK (receive edge) Setup Time
MOSI input to SCK (receive edge) Hold Time
SS input assertion to SCK setup
Table 118
Figure 53. SPI Slave Mode Timing
provide timing information for the SPI slave mode pins. Timing
T2
Input Data
T3
Output Data
Z8 Encore! XP
Product Specification
Minimum Maximum
Electrical Characteristics
2 * Xin
3 * Xin
1 * Xin
period
period
period
®
0
Delay (ns)
F64XX Series
period +
20 nsec
3 * Xin
232