Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 331

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Serial Errors
Interrupts
DBG pin used as a GPIO pin
The UARTEN control bit must be set to one to use the serial interface as a UART. Clearing
the UARTEN control bit to zero will prevent data received on the DBG pin from being
written to the Receive Data register. Clearing the UARTEN control bit to zero also 
prevents data written to the Transmit Data register from being transmitted on the single
pin interface.
If the UART is disabled, data is still written to the Receive Data register and read from the
Transmit Data register. These actions still generates UART interrupts. The UARTEN con-
trol bit only prevents data from being transmitted to or received from the DBG pin.
The serial interface detects the following error conditions:
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Transmission of data is prevented if the transmit collision, receive framing error, receive
break detect, receive overrun, or receive data register full status bits are set.
The Debug UART generates interrupts during the following conditions:
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The DBG pin is used as a GPIO pin. The serial interface cannot be used for debugging
when the DBG pin is configured as a GPIO pin. To set up the DBG pin as a GPIO pin,
software must clear the
Software uses the pin as an input by clearing the output enable control bit. The PIN status
bit in
The DBG pin is configured as an output pin by setting the output enable control bit. The
logic state of the IDLE bit in
pin.
Receive framing error (received Stop bit is Low).
Transmit collision (OCD releases the bus high to send a logic 1 and detects it is Low).
Receive overrun (received data before previously received data read).
Receive break detect (10 or more bits Low).
Receive Data register is Full (includes Rx Framing Error and Rx Overrun Error).
Transmit Data register is empty.
Auto-Baud Detector loads the BRG (auto-baud character received).
Receive Break detected.
Line Control Register (DBGLCR)
DBGUART
P R E L I M I N A R Y
Line Control Register (DBGLCR)
option bit and
reflects the state of the DBG pin.
OCDEN
control bit.
is driven onto the DBG
Product Specification
ZNEO
On-Chip Debugger
Z16F Series
315