Z16F6411FI20SG Zilog, Z16F6411FI20SG Datasheet - Page 70

• Manufacturer Part Number: Z16F6411FI20SG
• Description: IC ZNEO MCU FLASH 64K 80QFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F6411FI20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-BQFP
• Processor Series: Z16F6x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4571

PS022008-0810
Table 17. External Interface Timing for a Read Operation - ISA Mode
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
External Interface Read Timing - ISA Mode
Figure 15
performing a Read operation in ISA mode. In
state generator has been configured to provide 2 Wait states during Read operations. 
In
configured for active Low operation. The Read signal (RD) timing is shown for both
NORMAL and ISA modes.
Abbreviation
XIN Rise to Address Valid Delay
XIN Rise to Address Output Hold Time
Data Input Valid to XIN Rise Setup Time
XIN Rise to Data Input Hold Time
XIN Rise to CS Assertion Delay
XIN Rise to CS Deassertion Hold Time
XIN Fall to RD Assertion Delay
XIN Fall to RD Deassertion Hold Time
WAIT Input Pin Assertion to XIN Rise Setup Time
WAIT Input Pin Deassertion to XIN Rise Setup Time
XIN Rise to DMAACK Assertion Delay
XIN Rise to DMAACK Deassertion Hold Time
XIN Rise to BHEN or BLEN Assertion Delay
XIN Rise to BHEN or BLEN Deassertion Hold Time
Figure 15
on page 56 and
on page 56, it is also assumed that the chip select (CS) signals have been
Table 17
P R E L I M I N A R Y
provide timing information for the external interface
Figure 15
on page 56, it is assumed the Wait
Minimum
3
3
3
3
1
1
3
3
Delay (ns)
Product Specification
ZNEO
Maximum
External Interface
10
10
10
10
10
3
Z16F Series
55